公开(公告)号：EP1354410A2

公开(公告)日：2003-10-22

申请号：EP01977178.1

申请日：2001-09-26

Applicant: TERADYNE, INC.

Inventor： SHEEN, Timothy, W.

IPC: H03M3/04

CPC classification number: H03M3/322 ,  H03M3/50

Abstract: A circuit topology and method for converting a digital input signal to an analog output signal employs a modified sigma-delta loop and a DAC, and operates with improved accuracy over a wide frequency range. A loop filter such as a digital accumulator receives an input signal proportional to the difference between a digital input signal and a feedback signal. A quantizer quantizes the output of the loop filter, and the DAC converts the quantized signal into an analog output signal. The quantized signal is also provided to a DAC model. In response to the quantized signal and behavioral information about the DAC, the DAC model varies the feedback signal to match expected output signals from the DAC, including errors introduced by the DAC. By the operation of the sigma-delta loop, the errors of the DAC are substantially reduced.

公开(公告)号：EP2962392B1

公开(公告)日：2018-12-26

申请号：EP14708423.0

申请日：2014-02-20

Applicant: Microchip Technology Incorporated

Inventor： QUIQUEMPOIX, Vincent

IPC: H03K5/15

CPC classification number: H03M3/34 ,  H03K5/15 ,  H03M1/00 ,  H03M1/12 ,  H03M1/804 ,  H03M3/30 ,  H03M3/322 ,  H03M3/356 ,  H03M3/422

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.

公开(公告)号：EP3407500A1

公开(公告)日：2018-11-28

申请号：EP17172940.3

申请日：2017-05-25

Applicant: NXP B.V.

Inventor： Breems, Lucien Johannes ,  Bolatkale, Muhammed ,  Zhang, Chenming

IPC: H03M3/00

CPC classification number: H03M3/322 ,  H03M3/37 ,  H03M3/42 ,  H03M3/464 ,  H03M3/496

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, (300) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal (309) to a digital output signal (314); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal (309) such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal (314).

公开(公告)号：EP2782259A3

公开(公告)日：2015-01-07

申请号：EP14151925.6

申请日：2014-01-21

Applicant: Hamilton Sundstrand Corporation

Inventor： Courtney, Christopher J.

IPC: H03M1/64 ,  H03M1/06 ,  G01D5/20

CPC classification number: H03M1/645 ,  G01D5/2073 ,  G01P3/489 ,  H03M1/0617 ,  H03M1/485 ,  H03M3/322

Abstract: According to one aspect, a resolver-to-digital converter induces a first filter 208 configured to receive a first delta-sigina modulated resolver input. A second filter 210 is configured to receive a second delta-sigma modulated resolver input. A summing junction 216 is configured to output a difference between a scaled output of the first filter and a scaled output of the second filter. A controller 222 is configured to generate a controller output based on a product of a demodulator 226 and an output of the summing junction. An integrator 230 is configured to generate an estimated position based on the controller output. The resolver-to-digital converter also includes a compensator configured to generate a compensated estimated position based on the controller output and a compensation offset delay adjustment.

公开(公告)号：EP1810406B1

公开(公告)日：2013-01-02

申请号：EP05812383.7

申请日：2005-10-17

Applicant: Linear Technology Corporation

Inventor： OPRESCU, Florin A.

IPC: H03M1/00 ,  H03M3/02

CPC classification number: H03M3/322 ,  H03M3/43 ,  H03M3/456 ,  H03M3/496

公开(公告)号：EP1803223B1

公开(公告)日：2013-01-02

申请号：EP05810349.0

申请日：2005-10-17

Applicant: Linear Technology Corporation

Inventor： OPRESCU, Florin A.

IPC: H03M1/14

CPC classification number: H03M3/322 ,  H03M3/43 ,  H03M3/456 ,  H03M3/496

公开(公告)号：EP1999851A4

公开(公告)日：2012-06-13

申请号：EP07762710

申请日：2007-01-26

Applicant: FISHER ROSEMOUNT SYSTEMS INC

Inventor： WANG RONGTAI

IPC: H03M3/00 ,  G01D5/24 ,  G01L9/12 ,  H03M1/10

CPC classification number: H03M3/322 ,  G01L9/12 ,  H03M3/43 ,  H03M3/438

公开(公告)号：EP2337226A3

公开(公告)日：2012-05-23

申请号：EP10195269.5

申请日：2010-12-15

Applicant: Sanyo Electric Co., Ltd. ,  Sanyo Semiconductor Co., Ltd.

Inventor： Onishi, Akinobu

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M3/322 ,  H03M1/089 ,  H03M1/12 ,  H03M3/43 ,  H03M3/456

Abstract: A signal processing circuit includes: an AD converter configured to quantize an input signal, whose amplitude changes in accordance with temperature, within a set voltage range and convert the quantized input signal into a digital signal; and a setting circuit configured to set the voltage range so as to be wider when the input signal is greater in amplitude in accordance with the temperature and so as to be narrower when the input signal is smaller in amplitude in accordance with the temperature.

公开(公告)号：EP1993212B1

公开(公告)日：2010-07-14

申请号：EP08008875.0

申请日：2008-05-13

Applicant: Atmel Automotive GmbH

Inventor： Samid, Lourans ,  Dvorszky, Robert ,  Blatz, Werner ,  Schwarzmüller, Marco ,  Großkinsky, Ulrich

IPC: H04B1/40 ,  H03M1/12

CPC classification number: H03M3/322 ,  H03M3/40 ,  H03M3/41

公开(公告)号：EP1805898A2

公开(公告)日：2007-07-11

申请号：EP05812353.0

申请日：2005-10-17

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： OPRESCU, Florin A.

IPC: H03M7/00

CPC classification number: H03M3/322 ,  H03M3/43 ,  H03M3/456 ,  H03M3/496

Abstract: A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.