公开(公告)号：EP0206784A2

公开(公告)日：1986-12-30

申请号：EP86304774

申请日：1986-06-20

申请人： ADVANCED MICRO DEVICES INC

发明人： LAM HENG-MUN ,  KESWICK PAUL D

IPC分类号： G11C7/00 ,  G06F12/04 ,  G11C11/00

CPC分类号： G11C11/005

摘要： A high access speed memory for the internal storage of data and the addressable input/output transfer of data thereto, the memory comprising means for the dynamic storage of data, means for the static storage of data, and means for transferring data between the dynamic storage means and the static storage means. The intimate interfacing of the static and dynamic memories provides a high access speed pathway to the dynamically stored data while impacting minimally on sense amplification timing and the use of a redundant dynamic memory scheme.

公开(公告)号：EP0099473A3

公开(公告)日：1986-11-20

申请号：EP83105927

申请日：1983-06-16

申请人： International Business Machines Corporation

发明人： Kotecha, Harish N.

IPC分类号： G11C11/24 ,  G11C17/00

CPC分类号： G11C11/005 ,  G11C17/12 ,  H01L27/10805 ,  H01L27/112

摘要： A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device (ROS,) and a RAM FET device (RAM 1 ) are connected in common to a bit sensing line (BL2) connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line (BL2) indicating that a gate is present on the ROS FET device. A write driver circuit (32) is also connected to the bit sensing line (BL2), for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage. The charge storage element shares a common node with the ROS FET device and the RAM FET device and the sense amplifier is connected to the opposite side of the RAM FET device.

公开(公告)号：EP0037233B1

公开(公告)日：1985-09-25

申请号：EP81301251.5

申请日：1981-03-24

申请人： FUJITSU LIMITED

发明人： Nakano, Tomio ,  Takemae, Yoshihiro

IPC分类号： G11C11/24 ,  G11C8/00 ,  G11C11/40 ,  G11C5/02

CPC分类号： G11C11/005 ,  G11C5/025 ,  G11C7/065 ,  G11C8/12 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

公开(公告)号：EP0057784A3

公开(公告)日：1984-09-05

申请号：EP81304889

申请日：1981-10-20

申请人： BURROUGHS CORPORATION (a Michigan corporation)

发明人： Tuan, Hsing Ti

IPC分类号： G11C17/00 ,  G11C11/24

CPC分类号： G11C7/20 ,  G11C11/005 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108

摘要： The disclosed memory includes a semiconductor substrate having dopant atoms of a first conducivity type, a plurality of charge storage regions in the substrate, a conductive means over the charge storage regions, dopant atoms of a second conductivity type opposite to the first conductivity type disposed in a subset of the charge storage regions, and a means for selectively applying first and second voltages to the conductive means. With the first voltage applied to the conductive means, the memory operates in a read-only mode where data in the storage regions is fixed and is represented by the presence or absence of the second conductivity type dopant atoms; and with the second voltage applied, the memory operates as a read-write memory where data in the storage regions is variable and is independent of the presence or absence of the second conductivity type dopant atoms.

公开(公告)号：EP4393279A1

公开(公告)日：2024-07-03

申请号：EP22765063.7

申请日：2022-08-11

申请人： International Business Machines Corporation

发明人： XIE, Ruilong ,  REZNICEK, Alexander ,  WANG, Wei ,  LI, Tao ,  KANG, Tsung-Sheng

IPC分类号： H10B61/00 ,  H10N59/00 ,  G11C11/16

CPC分类号： G11C11/005 ,  G11C11/161 ,  G11C13/0004 ,  H10B61/10

公开(公告)号：EP1384231B1

公开(公告)日：2018-11-14

申请号：EP02766659.3

申请日：2002-04-26

申请人： Invensas Corporation

发明人： LEUNG, Wingyu ,  SIM, Jae-Kwang

IPC分类号： G11C5/00

CPC分类号： G11C11/005 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40618

摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.

公开(公告)号：EP3374874A1

公开(公告)日：2018-09-19

申请号：EP16865153.7

申请日：2016-11-11

申请人： Total Phase, Inc.

发明人： HOLDEN, Thomas, P. ,  SANTHANAM, Kumaran

IPC分类号： G06F13/00

CPC分类号： G06F9/455 ,  G06F9/4411 ,  G11C11/005 ,  G11C14/0009 ,  G11C14/0054

摘要： A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host.

公开(公告)号：EP3314364A1

公开(公告)日：2018-05-02

申请号：EP16814888.0

申请日：2016-05-16

申请人： Intel Corporation

发明人： DANG, Thi ,  BURNS, James S. ,  WUNDERLICH, Russell J. ,  COIMBATORE PREMKUMAR, Jagannath

IPC分类号： G06F1/32 ,  G06F12/06 ,  G06F3/06

CPC分类号： G11C5/147 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/005 ,  G11C11/2297 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

摘要： Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.

公开(公告)号：EP3268864A2

公开(公告)日：2018-01-17

申请号：EP16762610.0

申请日：2016-03-11

申请人： Rambus Inc.

发明人： WARE, Frederick ,  TSERN, Ely ,  LINSTADT, John

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C11/005

摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：EP3259582A1

公开(公告)日：2017-12-27

申请号：EP16704228.2

申请日：2016-02-12

申请人： Camlab Limited

发明人： SIMS, Stephen Charles

IPC分类号： G01N27/28 ,  G06F12/06 ,  G11C11/00 ,  H04W52/02 ,  H04W84/18

CPC分类号： G01N27/286 ,  G06F12/0238 ,  G06F12/0638 ,  G06F2212/202 ,  G06F2212/205 ,  G11C11/005 ,  H04Q9/00 ,  H04Q2209/43 ,  H04Q2209/826 ,  H04Q2209/88 ,  H04W52/0258 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144

摘要： A sensor interface for interfacing with a sensor such as an electrochemical sensor, a temperature sensor or the like in which the interface comprises a memory configured to store data received at the interface from a sensor. The sensor interface is configured to assess the difference between data values in the memory, and to transmit advertising packets at a rate dependent on the difference between the values. The sensor interface includes a volatile memory and a non-volatile memory. The volatile memory is configured to store data received at the sensor interface from a sensor. The non-volatile memory is configured to store data stored in the volatile memory. The sensor interface is configured such that: data received at the sensor is stored in the volatile memory forming stored data until the volatile memory is substantially full and then at least some of the stored data is transferred to the non-volatile memory.