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    Variable width content addressable memory device for searching variable with data
    41.
    发明公开
    Variable width content addressable memory device for searching variable with data 审中-公开
    Inhaltsadressierbare Speicherannnung变种器Breite zur Suche von Daten variabler Breite

    公开(公告)号：EP1083573A1

    公开(公告)日：2001-03-14

    申请号：EP00307759.1

    申请日：2000-09-08

    申请人： Sibercore Technologie, Inc.

    发明人： Gibson, Randall G. F. ,  Shafai, Farhad

    IPC分类号： G11C15/00 ,  G11C15/04 ,  G06F17/30

    CPC分类号： G06F7/74 ,  G11C15/00 ,  G11C15/04 ,  G11C29/14 ,  G11C29/26 ,  G11C29/816 ,  G11C2029/2602

    摘要： The present invention provides variable width CAM devices for searching data of variable widths. The CAM device includes a plurality of CAM blocks and a plurality of first encoders. The plurality of CAM blocks is configured to store a plurality of data of variable widths with each data having one or more data portions of one or more predetermined widths. Each CAM block is configured to store a predetermined width portion of the data such that each data is stored in one or more CAM blocks. The CAM blocks receive a search data having a specified number of search data portions with each search data portion having one or more predetermined widths. Each CAM block receives a search data portion of the search data for searching the search data in the CAM blocks. The plurality of dual mode first encoders is configured for concatenating the specified number of the CAM blocks to generate one or more search results. A set of the dual mode first encoders concatenates the specified number of CAM blocks to match the width of the search data. The remaining dual mode first encoders generate one or more search results when the concatenated CAM blocks contain data that matches the search data.

    摘要翻译： 本发明提供了用于搜索可变宽度数据的可变宽度CAM装置。 CAM装置包括多个CAM块和多个第一编码器。 多个CAM块被配置为存储可变宽度的多个数据，每个数据具有一个或多个预定宽度的一个或多个数据部分。 每个CAM块被配置为存储数据的预定宽度部分，使得每个数据被存储在一个或多个CAM块中。 CAM块接收具有指定数量的搜索数据部分的搜索数据，每个搜索数据部分具有一个或多个预定宽度。 每个CAM块接收用于搜索CAM块中的搜索数据的搜索数据的搜索数据部分。 多个双模式第一编码器被配置为连接指定数量的CAM块以产生一个或多个搜索结果。 一组双模式第一编码器连接指定数量的CAM块以匹配搜索数据的宽度。 当连接的CAM块包含与搜索数据匹配的数据时，剩余的双模式第一编码器生成一个或多个搜索结果。

    Semiconductor memory device having test circuit
    42.
    发明授权
    Semiconductor memory device having test circuit 失效
    与测试电路的半导体存储装置

    公开(公告)号：EP0617429B1

    公开(公告)日：2000-10-11

    申请号：EP94100993.8

    申请日：1994-01-24

    申请人： NEC CORPORATION

    发明人： Matsui, Yoshinori, c/o NEC Corporation

    IPC分类号： G11C29/00

    CPC分类号： G11C29/38 ,  G11C29/26 ,  G11C29/28

    摘要： A semiconductor memory device is disclosed which has a data output circuit including a first node, a second node, first and second transistors connected in series between the first node and a potential line, third and fourth transistors connected in series between the first node and the potential line, fifth and sixth transistors connected in series between the second node and the potential line, seventh and eighth transistors connected in series between the second node and the potential line, one of the first and third transistors being driven in response to a data signal read from a selected memory cell and one of the fifth and seventh transistors being driven in response to an inverted data signal of the data signal in a normal mode while turning one of the second and fourth transistor and one of the sixth and eighth transistors ON, both of the first and third transistors being driven in response to the data signal and both of the fifth and seventh transistors being driven in response to the inverted data signal while all the second, fourth, sixth and eighth transistors ON. The output circuit further includes an output logic circuit driving an output terminal to one of first and second logic levels when the first and second nods have logic levels different from each other and to a high impedance when the first and second nodes have logic levels equal to each other.

    Semiconductor memory device with a circuit
    44.
    发明公开
    Semiconductor memory device with a circuit 失效
    具有电路的半导体存储器件

    公开(公告)号：EP0569014A3

    公开(公告)日：1997-04-09

    申请号：EP93107367.0

    申请日：1993-05-06

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Kozuka, Eiji ,  Miyawaki, Naokazu

    IPC分类号： G11C29/00

    CPC分类号： G11C29/48 ,  G11C29/26

    摘要： A semiconductor memory device has a plurality of memory cell arrays (12a,12b); input and output sections (11a, 11b) each provided so as to correspond to each of the memory cell arrays; and an allocating section (17) provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.

    Semiconductor memory device
    48.
    发明公开
    Semiconductor memory device 失效

    公开(公告)号：EP0156345A3

    公开(公告)日：1988-07-27

    申请号：EP85103494

    申请日：1985-03-26

    申请人： FUJITSU LIMITED

    发明人： Ooami, Kazuo ,  Sugo, Yasuhisa ,  Takeshima, Tohru

    IPC分类号： G11C07/00 ,  G11C11/40

    CPC分类号： G11C29/26 ,  G11C8/12 ,  G11C11/416 ,  G11C29/36

    摘要： A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and means for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

    Verfahren zum Betreiben eines Halbleiterspeichers mit integrierter Paralleltestmöglichkeit und Auswerteschaltung zur Durchführung des Verfahrens
    50.
    发明公开
    Verfahren zum Betreiben eines Halbleiterspeichers mit integrierter Paralleltestmöglichkeit und Auswerteschaltung zur Durchführung des Verfahrens 失效
    操作具有集成并行测试能力和评价电路的半导体存储器，用于执行该方法的方法。

    公开(公告)号：EP0197363A1

    公开(公告)日：1986-10-15

    申请号：EP86103574.9

    申请日：1986-03-17

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Kantz, Dieter, Dipl.-Ing. ,  Kuchinke, Günther, Dipl.-Ing.(FH)

    IPC分类号： G06F11/26 ,  G11C29/00

    CPC分类号： G11C29/26

    摘要： In einem Testbetrieb Lesen wird innerhalb des Halbleiterspeichers jedes der über Datenleitungen - (DL) aus Zellenfeldern (ZF) parallel ausgelesenen Testdaten mit einem Vergleichsdatensignal (DI T ) verglichen, das den Testdaten entspricht. Das Testen des Halbleiterspeichers wird also nicht in einem angeschlossenen Testautomaten, sondern innerhalb des Halbleiterspeichers mittels einer Auswerteschaltung (AS) durchgeführt. Diese enthält eine aus Valenzschaltungen (VS) aufgebaute erste Vergleichsschaltung (VS1), eine zweite Vergleichsschaltung - (VS2) und eine Ergebnisschaltung (ES). Beispielsweise am Datenausgangsanschluß (D o ) liegt dann in dem Falle, in dem der Halbleiterspeicher in Ordnung ist (Gutfall), das Vergleichsdatensignal (DI T an. Es kann auch ein festes Potential wie logisch "1" oder logisch "0" anliegen. Im Fehlerfall liegt ein dazu komplementäres Signal an.

    摘要翻译： 在测试模式中平行于经由数据线的比较数据信号（DIT）读出的测试数据读取每个（DL）单元阵列（ZF）的对应于测试数据的半导体存储器内进行比较。 半导体存储器的测试中，因此不会通过评估电路（AS）的装置在连接测试槽进行，但在半导体存储器内。 这包含从构造的Valenzschaltungen（VS）第一比较器电路（VS1），第二比较器电路（VS2）和结果电路（ES）。 例如，在数据输出端（Do）为然后在所述半导体存储器是为了情况下（肯定的情况下），所述比较数据信号（DIT中。它也可以是一个固定电势，如逻辑“1”或逻辑“0”上。是发生了错误， 互补信号。