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83 条记录 (耗时 0.023 秒)

    CLOCK DISTRIBUTION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
    41.
    发明公开
    CLOCK DISTRIBUTION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF 审中-公开

    公开(公告)号：EP3146402A4

    公开(公告)日：2018-01-24

    申请号：EP15795872

    申请日：2015-05-14

    申请人： FLEX LOGIX TECH INC

    发明人： WANG CHENG C

    IPC分类号： G06F1/10 ,  H03K19/177

    CPC分类号： H03K19/1774 ,  G06F1/08 ,  G06F1/10 ,  H03K19/17724 ,  H03K19/17744 ,  H03K19/17748

    摘要： An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.

    FIELD PROGRAMMABLE GATE ARRAY AND COMMUNICATION METHOD
    42.
    发明公开
    FIELD PROGRAMMABLE GATE ARRAY AND COMMUNICATION METHOD 审中-公开
    FELDPROGRAMMIERBARE GATE-ANORDNUNG UND KOMMUNIKATIONSVERFAHREN

    公开(公告)号：EP3118747A1

    公开(公告)日：2017-01-18

    申请号：EP14887727.7

    申请日：2014-04-03

    申请人： Huawei Technologies Co., Ltd.

    发明人： YANG, Weiguo ,  TU, Jun ,  WANG, Zuo

    IPC分类号： G06F13/38

    CPC分类号： G06F13/4027 ,  G06F13/4022 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

    摘要： The application provides a field programmable gate array FPGA and a communication method. At least one application specific integrated circuit ASIC-based hard core used for communication and interconnection is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay. A source functional module sends data to a station; the station sends the data to the high-speed exchange and interconnection unit; and the high-speed exchange and interconnection unit sends the data to a destination functional module by using a station connected to the destination functional module. In this way, data is transmitted between the source functional module and the destination functional module.

    摘要翻译： 该应用提供了现场可编程门阵列FPGA和通信方法。 FPGA中嵌入至少一个专用集成电路基于ASIC的硬核，用于通信和互连。 基于ASIC的硬核包括高速交换和互连单元以及至少一个站。 每个站连接到高速交换和互连单元。 该站被配置为在FPGA中的每个功能模块和基于ASIC的硬核之间传输数据。 高速交换和互连单元被配置为在站之间传输数据。 在应用提供的FPGA中，嵌入了基于ASIC的硬核，可以促进每个功能模块与基于ASIC的硬核之间的数据交换，并减少时间延迟。 源功能模块向站发送数据; 该站将数据发送到高速交换和互连单元; 并且高速交换和互连单元通过使用连接到目的地功能模块的站将数据发送到目的地功能模块。 以这种方式，在源功能模块和目的功能模块之间传输数据。

    LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD
    47.
    发明公开
    LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD 审中-公开
    LOGIKBLOCK-STEUERSYSTEM UND LOGIKBLOCK-STEUERVERFAHREN

    公开(公告)号：EP1953916A1

    公开(公告)日：2008-08-06

    申请号：EP06832685.9

    申请日：2006-11-15

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： ICHINOMIYA, Takahiro c/o Matsushita Electric Industrial Co., Ltd.

    IPC分类号： H03K19/173 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K5/15

    CPC分类号： H03K19/1774 ,  H03K19/17784

    摘要： The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of alogicblock, a gated clock technique, apower-off technique, or the like is used.

    摘要翻译： 获得在可编程逻辑单元中执行目标处理时可以停止的块的数量，并且计算包括在可编程逻辑单元中的多个逻辑块中的每一个的停止率。 以停止率的升序从多个逻辑块中选择与可停止的块相同数量的逻辑块，所选择的逻辑块被确定为其操作将被停止的逻辑块，并且操作是 停止。 作为停止alogicblock的操作的技术，使用门控时钟技术，apower-off技术等。

    SPARE CELL ARCHITECTURE FOR FIXING DESIGN ERRORS IN MANUFACTURED INTEGRATED CIRCUITS
    48.
    发明公开
    SPARE CELL ARCHITECTURE FOR FIXING DESIGN ERRORS IN MANUFACTURED INTEGRATED CIRCUITS 审中-公开
    ERSATZZENENARCHITEKURURZUR REPARATUR VON KONSTRUKTIONSFEHLERN IN INTEGRIERTEN SCHALTKREISEN

    公开(公告)号：EP1568133A4

    公开(公告)日：2005-11-30

    申请号：EP03759356

    申请日：2003-09-17

    申请人： ATMEL CORP

    发明人： VERGNES ALAIN

    IPC分类号： G06F11/20

    CPC分类号： H03K19/17764 ,  H03K19/1774 ,  H03K19/17796

    摘要： A fully self-sufficient configurable spare gate cell (11) has two types of inputs: a functional input bus (FIN; 10,12; 68; 76) and an equation input bus (EQ.IN; 70; 78), whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. The spare cell may also include a D flip-flop (38; 84). In a spare state, the functional input buses are connected to an area of pre-defined logic (64) where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

    摘要翻译： 完全自给自足的可配置备用栅极单元（11）具有两种类型的输入：功能输入总线（FIN; 10,12; 68; 76）和方程式输入总线（EQ.IN; 70; 78），其中 通过向方程式输入总线发送某些信号，可以将备用门单元转换成产品操作员的任意总和。 备用单元还可以包括D触发器（38; 84）。 在备用状态下，功能输入总线连接到预定义逻辑（64）的区域，其中对错误修复的需要很高。 因此，在芯片设计的放置和布线阶段，备用单元将自动放置在靠近错误修复区域的位置，从而减少寻找路由通道的需求。