公开(公告)号：EP4142159A1

公开(公告)日：2023-03-01

申请号：EP21192687.8

申请日：2021-08-23

申请人： Socionext Inc.

发明人： SANTHOSH KUMAR, Sandeep ,  KUMAR, Jayaraman ,  JALILI SEBARDAN, Armin ,  WILSON, Martin

IPC分类号： H03M1/08 ,  H03M1/40 ,  H03M1/46 ,  H03M1/06 ,  H03M1/80

摘要： Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry.

公开(公告)号：EP3570436B1

公开(公告)日：2021-10-06

申请号：EP19174769.0

申请日：2019-05-15

发明人： Garrity, Douglas Alan ,  Hoseini, Mariam ,  Braswell, Brandt ,  Kabir, Mohammad Nizam

IPC分类号： H03F3/00 ,  H03F3/45 ,  H03M1/16 ,  H03M1/06 ,  H03M1/40 ,  H03M1/44

公开(公告)号：EP3716487A1

公开(公告)日：2020-09-30

申请号：EP19165614.9

申请日：2019-03-27

申请人： NXP B.V.

发明人： Olieman,, Erik ,  Litjes,, Alphons ,  van der Dussen,, Leon

IPC分类号： H03M1/40 ,  H03M1/80 ,  H03M1/46

摘要： A capacitive sampling circuit (330) comprises: a first-differential-input-terminal (304), configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal (302), configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal (305), configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors (320), each having a first-plate (334) and a second-plate (336); a plurality of reference-voltage-terminals (332), each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block (326) configured to selectively connect the first-plate (334) of each of the plurality of first-sampling-capacitors (320) to either: (i) the first-differential-input-terminal (304); or (ii) a respective one of the plurality of reference-voltage-terminals (332); and a first-capacitor-second-plate-switch (327), configured to selectively connect or disconnect the second-plate (336) of each of the plurality of first-sampling-capacitors (320) to the second-differential-input-terminal (302).

公开(公告)号：EP3567720A1

公开(公告)日：2019-11-13

申请号：EP19166889.6

申请日：2019-04-02

申请人： NXP USA, Inc.

发明人： Hoseini, Mariam ,  Garrity, Douglas Alan ,  Kabir, Mohammad Nizam ,  Braswell, Brandt

IPC分类号： H03F3/00 ,  H03F3/45 ,  H03M1/44 ,  H03M1/40 ,  H03M1/06 ,  G11C27/02

摘要： A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.

公开(公告)号：EP3562041A1

公开(公告)日：2019-10-30

申请号：EP19162693.6

申请日：2019-03-13

申请人： INTEL Corporation

发明人： EITAN, Roee ,  LIVNE, Ram ,  KHAIRI, Ahmad ,  KRUPNIK, Yoel ,  COHEN, Ariel

IPC分类号： H03M1/46 ,  H03M1/40 ,  H03K3/356

摘要： An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

公开(公告)号：EP3487077A1

公开(公告)日：2019-05-22

申请号：EP17202502.5

申请日：2017-11-20

申请人： NXP B.V.

发明人： Van VELDHOVEN, Robert ,  LITJES, Alphons ,  OLIEMAN, Erik

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/08 ,  H03M1/40 ,  H03M1/80

摘要： The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

公开(公告)号：EP3343775A1

公开(公告)日：2018-07-04

申请号：EP17209103.5

申请日：2017-12-20

申请人： MediaTek Inc.

发明人： LIU, Chun-Cheng

IPC分类号： H03M1/08 ,  H03M1/12 ,  H03M1/40 ,  H03M3/00 ,  H03M1/46

CPC分类号： H03M1/0854 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468

摘要： An interleaving successive approximation analog-to-digital converter (SAR ADC) with noise shaping having a first SAR block, a second SAR block, and a noise-shaping circuit is provided. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block.

公开(公告)号：EP2571169A4

公开(公告)日：2016-03-16

申请号：EP11780708

申请日：2011-05-13

申请人： UNIV SHIZUOKA NAT UNIV CORP

发明人： KAWAHITO SHOJI

IPC分类号： H03M1/14 ,  H03M1/16 ,  H03M1/40 ,  H03M1/56 ,  H04N5/357 ,  H04N5/378

CPC分类号： H03M1/12 ,  H03M1/145 ,  H03M1/162 ,  H03M1/403 ,  H03M1/56 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/378

摘要： An object is to provide an A/D converter which uses a plurality of A/D converter circuits and can lower the A/D conversion accuracy in the A/D converter circuit for a lower digit by employing a cyclic A/D conversion scheme for an upper digit thereof. An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to 1/2 L that in the A/D converter circuit 103.

公开(公告)号：EP1989781B1

公开(公告)日：2009-06-24

申请号：EP06728459.6

申请日：2006-02-27

申请人： STMicroelectronics S.r.l.

发明人： CESURA, Giovanni Antonio ,  MASSOLINI, Roberto Giampiero

IPC分类号： H03M1/10 ,  H03M1/40 ,  H03M1/44 ,  H03M1/16

CPC分类号： H03M1/1061 ,  H03M1/1004 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

摘要： Multistage ADC (1) for converting in multi- step cycles, analogue samples (V] n) of an input signal (VIn) into digital codes (Dout) each cycle resolving at least one bit of digital code (Dout), the converter (1) including: - a generation block (3) of a pseudorandom sequence (Y' ts) to be summed to said analogue samples, obtaining a second sequence ( V+in) of analog samples; - conversion means (5) with controllable digital gain ( g ), receiving the second sequence (V+in) and outputting bits of said digital codes (Dout); - a feedback loop (2, 6, 7, 8) for performing said multi- step conversion cycles, with a loop gain (GLoop); - a digital calibration block (9) matching the digital gain ( g ) to the loop gain ( GLoop ); said second sequence (V+in) including predetermined samples with no contribution of said pseudorandom sequence (?-ts); - a prediction block (10) to produce a digital estimation (Dout) of said input signal (Vin).

公开(公告)号：EP1759461B1

公开(公告)日：2008-12-24

申请号：EP05745163.5

申请日：2005-06-08

申请人： NXP B.V.

发明人： KARAVIDAS, Dimitrios ,  DE CREMOUX, Guillaume ,  RISTIC, Sasa ,  CHRISTOFOROU, Yovgos

IPC分类号： H03M1/40

CPC分类号： H03M1/403 ,  H03M1/1014

摘要： Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.