公开(公告)号：EP1211731A3

公开(公告)日：2006-08-02

申请号：EP01123177.6

申请日：2001-09-27

申请人： Saifun Semiconductors Ltd.

发明人： Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C11/56

CPC分类号： H01L27/11568 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory array includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line.

公开(公告)号：EP1679721A2

公开(公告)日：2006-07-12

申请号：EP06100056.8

申请日：2006-01-04

申请人： Saifun Semiconductors Ltd.

发明人： Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C29/028 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/50 ,  G11C29/50004

摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

摘要翻译： 一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元置于预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数 第一个单元到第一个工作脉冲。

公开(公告)号：EP1443521A2

公开(公告)日：2004-08-04

申请号：EP04250527.1

申请日：2004-01-30

申请人： Saifun Semiconductors Ltd

发明人： Eisen, Shai ,  Varkony, Roni ,  Edan, Mori

IPC分类号： G11C16/10 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C16/26

摘要： A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

摘要翻译： 一种用于操作存储单元阵列的方法，所述方法包括：将存储单元阵列的字线作为从高速缓冲存储器写入数据集的地址，以及通过写入所述特定组的第一块来对所述数据集进行加扰的地址 从高速缓冲存储器到数组的第一字线的数据，以及将特定数据集的第二块从高速缓冲存储器写入阵列的第二字线，第一块包括特定集合的第一子集 的数据，并且所述第二块包括所述特定数据集合的第二子集。

公开(公告)号：EP1225596A3

公开(公告)日：2003-07-23

申请号：EP01309289.5

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Bloom, Ilan ,  Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5634

摘要： A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

公开(公告)号：EP1248263A1

公开(公告)日：2002-10-09

申请号：EP02252406.0

申请日：2002-04-03

申请人： Saifun Semiconductors Ltd

发明人： Maayan, Eduardo ,  Eliyahu, Ron ,  Lann, Ameet ,  Eitan, Boaz

IPC分类号： G11C7/14 ,  G11C16/28

CPC分类号： G11C16/14 ,  G11C7/062 ,  G11C7/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3468

摘要： A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

摘要翻译： 氮化物ROM（NROM）参考单元通过以大步骤升高漏极电压直到高于阈值中间电压来进行快速脉冲编程。 然后以一小段步骤将固定的漏极电压缓慢编程，直到最终目标电平高于最终目标电平，其中临时目标电平低于最终电平100-400mV，但大于从脉冲提高的预期阈值电压。 在每个编程脉冲之后测量阈值电压电平。

公开(公告)号：EP1227501A2

公开(公告)日：2002-07-31

申请号：EP01309290.3

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Avni, Dror ,  Eitan, Boaz

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

摘要翻译： 用于编程和擦除存储器阵列的方法包括将编程或擦除脉冲适配到存储器阵列的当前状态的步骤。 在一个实施例中，适配步骤包括以下步骤：确定用于对存储器阵列的快速位进行编程的编程脉冲的电压电平，并将存储器阵列的初始编程电平设置为程序的一般附近的电平 水平的快速位。 为了擦除，该方法包括以下步骤：确定用于擦除所述存储器阵列的缓慢擦除位的擦除脉冲的擦除条件，并将所述存储器阵列的初始擦除条件设置为所述缓慢擦除位的所述擦除条件的附近。 在阵列的另一实施例中，适配步骤包括以下步骤：将位的电流阈值电平测量到给定范围内，并根据测量的电流选择位的下一个编程或擦除脉冲的增量电压电平 门限等级。

公开(公告)号：EP1141964A1

公开(公告)日：2001-10-10

申请号：EP00901890.4

申请日：2000-02-03

申请人： Saifun Semiconductors Ltd.

发明人： EITAN, Boaz

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/26

摘要： A method for detecting the content of a selected memory cell (106) in a memory cell array (100) includes the steps of charging a drain of the selected memory cell to a ground potential, charging a source of the selected memory cell to a predetermined voltage potential (V1), detecting the voltage level on the drain and comparing the detected voltage level with a reference voltage level (Vreference), thereby producing a comparison result.

公开(公告)号：EP1091418A2

公开(公告)日：2001-04-11

申请号：EP00308781.4

申请日：2000-10-05

申请人： Saifun Semiconductors Ltd

发明人： Eitan, Boaz

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： A nitride programmable read only memory (NROM) cell has an oxide-nitride-oxide (ONO) layer (109, 110, 111) over at least a channel (100) and a pocket implant (120) self-aligned to at least one bit line junction (102). The cell also includes at least one area of hot electron injection within the ONO layer and over the pocket implant and at least one area of hot hole injection generally self-aligned to the area of hot electron injection.

摘要翻译： 氮化物可编程只读存储器（NROM）单元在至少一个通道（100）上的氧化物 - 氧化物 - 氧化物（ONO）层（109,110,111）和与至少一个自对准存储器 位线结（102）。 电池还包括在ONO层内和袋口注入物上的至少一个热电子注入区域，以及通常自热对准热电子注入区域的至少一个热空穴注入区域。

公开(公告)号：EP1010182A4

公开(公告)日：2000-09-27

申请号：EP98936654

申请日：1998-08-02

申请人： SAIFUN SEMICONDUCTORS LTD

发明人： EITAN BOAZ

IPC分类号： H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7887 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28282 ,  H01L29/7885 ,  H01L29/7923

摘要： A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bitS of information having a nonconducting charge trapping dielectric, such as silicon nitride (20), sandwiched between two silicon dioxide layers (18, 22) acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The noncoducting dielectric layer functions as an electrical charge trapping medium. A conducting gate electrode (24) is placed over the upper silicon dioxide layer (22). A left and right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

摘要翻译： 一种非易失性电可擦除可编程只读存储器（EEPROM），其能够存储具有不导电的电荷捕捉介电,:诸如氮化硅，夹在作为电绝缘体被游离缺失盘两个二氧化硅层之间的信息的两个比特。 本发明包括编程的方法，读取和擦除的两个比特EEPROM器件。 非导电的介电层用作对电电荷捕捉介质。 的导电栅极层被放置在所述上​​二氧化硅层。 左和右位被分别存储在电荷俘获层，邻近存储器单元的左侧和右侧区域的物理上不同的区域，。 所述存储器装置中的每一位进行编程以常规方式，利用热电子编程，通过施加编程电压至栅极和左或右区域，而另一个区域是接地的。 热电子被加速到足以被注入到接近在编程电压施加到所述捕捉介电层的区域中。 的装置，但是，在从上面写相反的方向读出，这意味着电压被施加到栅极和右侧或左侧区域，而另一个区域是接地的。 两个比特都能够被编程和读取，由于相对低的栅极电压与在相反方向上读取的组合。 这大大减少了跨越陷阱电荷区的潜力。 这通过扩增被困在与每个比特相关联的局部捕集区中的电荷的作用允许更短的编程时间。 此外，所述存储器单元的这两个位可以通过施加合适的独立擦除电压到栅被擦除和左或右的区域，以使从相应的电荷捕捉氮化物层的区域中移除电子。

公开(公告)号：EP0914658A1

公开(公告)日：1999-05-12

申请号：EP97927356.0

申请日：1997-06-24

申请人： Saifun Semiconductors Ltd

发明人： EITAN, Boaz

IPC分类号： G11C16 ,  G11C11 ,  H01L29

CPC分类号： H01L29/792 ,  G11C11/5671 ,  G11C16/0475

摘要： A novel apparatus and method for programming and reading a programmable read only memory (EPROM) having a trapping dielectric layer (20) sandwiched between two silicon dioxide layers (18, 20) is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric material are silicon oxide-silicon, nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charging trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer (24) is placed over the upper silicon dioxide layer (22). The memory device (10) is programmed in the conventional manner. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate (24) and the source (14) while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region.