公开(公告)号：EP1550879A1

公开(公告)日：2005-07-06

申请号：EP04030705.0

申请日：2004-12-23

申请人： TERADYNE, INC.

发明人： Ostertag, Edward

IPC分类号： G01R31/319

CPC分类号： G01R31/31919 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928

摘要： A channel architecture for use in automatic test equipment is disclosed. The channel architecture comprises pattern generation circuitry and timing circuitry responsive to the pattern generation circuitry to generate timing signals. Formatting circuitry coupled to the output of the timing circuitry generates pulse waveforms for application to pin electronics circuitry. The pin electronics circuitry is responsive to the formatting circuitry for interfacing the automatic test equipment to a device-under-test. The pattern generation circuitry, the timing circuitry, the formatting circuitry and the pin electronics circuitry are formed on the same integrated circuit.

摘要翻译： 公开了一种用于自动测试设备的通道架构。 信道架构包括响应于模式产生电路的模式产生电路和定时电路以产生定时信号。 耦合到定时电路的输出的格式化电路产生用于应用于引脚电子电路的脉冲波形。 引脚电子电路响应于格式化电路，用于将自动测试设备连接到被测器件。 图案生成电路，定时电路，格式化电路和引脚电子电路形成在同一集成电路上。

公开(公告)号：EP1550877A1

公开(公告)日：2005-07-06

申请号：EP04030706.8

申请日：2004-12-23

申请人： TERADYNE, INC.

发明人： Gohel, Tushar K.

IPC分类号： G01R31/28 ,  G01R31/319

CPC分类号： G01R31/31926 ,  G01R31/31924

摘要： A programmable active load is adapted for use with differential signals. The differential active load includes a diode quad having four terminals. A first programmable current source is connected to the first node and a second programmable current source is connected to the second node. The third and fourth nodes are respectively adapted to receive first and second differential signals of a differential pair of signals. The differential active load sources current to the more negative of the first and second differential signals, and sinks current from the more positive of the first and second differential signals.

摘要翻译： 可编程有源负载适用于差分信号。 差分有源负载包括具有四个端子的二极管四极管。 第一可编程电流源连接到第一节点，第二可编程电流源连接到第二节点。 第三和第四节点分别适于接收差分信号对的第一和第二差分信号。 差分有源负载源电流到第一和第二差分信号的负值更大，并且从第一和第二差分信号的正向吸收电流。

公开(公告)号：EP1371995B1

公开(公告)日：2005-04-06

申请号：EP03100960.8

申请日：2003-04-10

申请人： Agilent Technologies, Inc.

发明人： LIEBAU Henrik, Agilent Technologies Deutschland ,  DIPPON Thomas, Agilent Technologies Deutschland

IPC分类号： G01R31/319

CPC分类号： G01R31/31926

公开(公告)号：EP0859367B1

公开(公告)日：2004-10-06

申请号：EP98400378.0

申请日：1998-02-17

申请人： SCHLUMBERGER TECHNOLOGIES, INC.

发明人： Eastburn, Martin H.

IPC分类号： G11C29/00 ,  G06F11/263 ,  G06F11/273 ,  G01R31/319

CPC分类号： G01R31/31813 ,  G01R31/31926

公开(公告)号：EP1426780A2

公开(公告)日：2004-06-09

申请号：EP03257665.4

申请日：2003-12-05

申请人： Samsung Electronics Co., Ltd.

发明人： Choi, Jung-hwan

IPC分类号： G01R31/319

CPC分类号： G01R31/31926

摘要： Semiconductor devices with simultaneous bi-directional (SBD) data ports, test board configurations for such devices, and test methods for such devices, are disclosed. The devices have two SBD data ports with a pass mode that relays data between the ports. Significantly, each device contains configurable switching elements that allow a test mode, wherein unidirectional input/output data on one SBD data port is mapped to bi-directional data on the other SBD data port. This allows device testing with automated test equipment that employs unidirectional data signaling, and yet allows such test equipment to test the SBD capability of such devices.

摘要翻译： 在同时双向（SBD）的数据端口，用于寻求器件的测试板的配置，以及用于搜索的装置的测试方法的半导体器件，是游离缺失盘。 这些器件具有与合适的方式2个SBD数据端口那样端口之间中继数据。 显著，每个装置包含可配置的开关元件确实允许测试模式，worin一个SBD数据端口上的单向输入/输出数据被映射到其它SBD数据端口上的双向数据，这允许与自动化测试设备装置测试没有采用单向 数据信令，并且还允许在搜索的测试设备来测试搜索设备的SBD能力。

公开(公告)号：EP1394560A3

公开(公告)日：2004-04-14

申请号：EP03016802.5

申请日：2003-07-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kim, Hong-Beom ,  Park, Ho-Jin ,  In, Sung-Hwan ,  Kim, Ha-II

IPC分类号： G01R31/319 ,  G06F11/273

CPC分类号： G06F11/2733 ,  G01R31/31908 ,  G01R31/31926

摘要： A semiconductor chip test system and test method thereof are provided. The system comprises a plurality of data input/output pins (I/O), a tester (20) for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips (24) to be tested by the tester; a control circuit (22) for sequentially outputting the output data from each of the plurality of semiconductor chips to the tester during a read operation and simultaneously supplying the input data from the tester to the semiconductor chips during a write operation.

摘要翻译： 提供半导体芯片测试系统及其测试方法。 该系统包括多个数据输入/输出引脚（I / O），用于通过多个数据输入/输出引脚输入/输出数据的测试器（20） 多个待测试的半导体芯片（24）; 控制电路（22），用于在读取操作期间将多个半导体芯片中的每一个的输出数据顺序地输出到测试器，并且在写入操作期间同时将来自测试器的输入数据提供给半导体芯片。

公开(公告)号：EP1352256A2

公开(公告)日：2003-10-15

申请号：EP02720781.0

申请日：2002-01-10

申请人： ANALOG DEVICES, INCORPORATED

发明人： BABCOCK, Douglas, W.

IPC分类号： G01R31/28

CPC分类号： G01R31/31924 ,  G01R31/31926

摘要： A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver (134) includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal (VIL, VIH) via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

公开(公告)号：EP1255202A2

公开(公告)日：2002-11-06

申请号：EP02368046.5

申请日：2002-05-02

申请人： Megic Corporation

发明人： Mou-Shiung, Lin

IPC分类号： G06F13/38

CPC分类号： H01L25/0657 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/31905 ,  G01R31/31926 ,  G06F13/385 ,  H01L23/60 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

摘要翻译： 多集成电路芯片结构提供了结构的集成电路芯片之间的片上通信，没有ESD保护电路，没有输入/输出电路。 芯片间通信在集成电路芯片的内部电路之间。 该多集成电路芯片结构具有一个芯片间接口电路，用于选择性地将集成电路的内部电路连接到具有ESD保护电路和设计为在测试和老化过程期间与外部测试系统进行通信的输入/输出电路的测试接口电路。 多个互连的集成电路芯片结构具有安装到一个或多个第二集成电路芯片的第一集成电路芯片，以将集成电路芯片彼此物理和电连接。 第一集成电路芯片具有彼此连接的芯片间接口电路，以在每个集成电路芯片的内部电路连接到彼此的集成电路芯片的内部电路或测试接口电路之间选择性地通信，以在测试期间向所述内部电路提供刺激和响应 程序。 模式选择器接收芯片外部的信号，以确定通信是否与其他连接的集成电路芯片中的一个或单芯片模式（例如与测试接口电路）通信。 ESD保护被添加到模式选择器电路。

公开(公告)号：EP1249026A1

公开(公告)日：2002-10-16

申请号：EP01942786.3

申请日：2001-01-16

申请人： CREDENCE SYSTEMS CORPORATION

发明人： WOHLFARTH, Paul, Dana ,  HALE, Robert, R. ,  ELLIS, Travis, Scott

IPC分类号： H01H7/00 ,  G01R31/02

CPC分类号： H01H51/28 ,  G01R31/3004 ,  G01R31/31926 ,  G01R31/3193 ,  H01H49/00 ,  H01H50/10 ,  H01H50/44 ,  H01H51/281

摘要： A relay (70) includes contacts (73) residing within a glass tube (72). A coil (76) surrounding the tube (72) and a switch (66) are connected in parallel between two terminals (77) of the relay (70). A current source supplies a current to the coil (76) and switch (66). When the switch (66) is open, substantially all of the current passes through the coil (76) and the coil (76) produces a sufficient amount of magnetic flux to close the relay's contacts (73). When the switch (66) closes, it shunts a sufficient amount of the current away from the coil (76) to reduce the magnetic flux it produces below the level needed to keep the contacts (73) closed. The current source is sized so that the coil (76) requires relatively few turns, thereby allowing the relay (70) to be relatively thin. The coil (76) is formed by a conductor (140) embedded in an insulating substrate (128) surrounding the tube (72).

公开(公告)号：EP1088239A1

公开(公告)日：2001-04-04

申请号：EP99938179.1

申请日：1999-06-11

申请人： Infineon Technologies AG

发明人： SCHMID, Wilhelm ,  DÖRRHÖFER, Carsten

IPC分类号： G01R31/317

CPC分类号： G01R31/31708 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318572 ,  G01R31/31926

摘要： According to the invention, one or more external test connection contact points (pads; pins; balls), (2, 3) are provided in an integrated circuit component (chip) (1), through which signals (4, 5, 6) that are to be measured or analyzed are selectively fed, e.g. by means of a multiplex circuit (7, 8), and wherein the signals may be connected by means of routes located internally in the component from switch points that are not directly accessible, e.g. points inside the chip (15 to 20) or covered contact points. The device according to the invention is particularly useful for highly integrated semiconductor chips.