公开(公告)号：EP0044400B1

公开(公告)日：1986-10-08

申请号：EP81104335.5

申请日：1981-06-05

申请人： International Business Machines Corporation

发明人： Fatula, Joseph John, Jr. ,  Garbarino, Paul Louis

IPC分类号： H01L27/10 ,  H01L21/82 ,  G11C11/24

CPC分类号： H01L27/10861 ,  H01L21/30608 ,  H01L21/3065 ,  H01L27/10829 ,  H01L29/945

公开(公告)号：EP3296727A1

公开(公告)日：2018-03-21

申请号：EP16306195.5

申请日：2016-09-19

申请人： Murata Integrated Passive Solutions

发明人： VOIRON, Frédéric

IPC分类号： G01N27/00 ,  G01N33/483 ,  G01R29/00 ,  H01L27/00

CPC分类号： G01N33/4836 ,  G01R29/00 ,  H01L27/0805 ,  H01L29/945

摘要： An electrical stimulation and monitoring device comprises several signal paths which are connected in parallel with each other, and each containing a stimulation or sensing electrode (25, 35), a DC-blocking capacitor and a stimulation or sensing channel (26, 36). A semiconductor substrate (100) used for hosting the DC-blocking capacitors is connected electrically to a DC voltage source (2) through a substrate holding capacitor. Such substrate holding capacitor reduces a blanking time between stimulation and sensing periods, and also reduces cross-couplings between different ones of the signal paths while all the DC-blocking capacitors are provided on one and same semiconductor substrate.

摘要翻译： 电刺激和监测装置包括彼此并联连接的多个信号路径，每个信号路径包含刺激或感测电极（25,35），隔直流电容器和刺激或感测通道（26,36）。 用于容纳DC隔离电容器的半导体衬底（100）通过衬底保持电容器电连接到DC电压源（2）。 这种衬底保持电容器减少了刺激和感测周期之间的消隐时间，并且还减少了不同信号路径之间的交叉耦合，而所有隔直流电容器都设置在同一个半导体衬底上。

公开(公告)号：EP3088354B1

公开(公告)日：2017-11-08

申请号：EP16156215.2

申请日：2016-02-17

申请人： Honeywell International Inc.

发明人： YOUNGNER, Daniel

IPC分类号： B82Y10/00 ,  G06N99/00 ,  G21K1/00 ,  H01J49/00 ,  H01L29/94 ,  G04F5/14 ,  H01J3/38 ,  H01J9/14

CPC分类号： H01J3/38 ,  B82Y10/00 ,  G06N99/002 ,  G21K1/00 ,  H01J9/14 ,  H01J49/0018 ,  H01L29/945

摘要： Apparatuses, systems, and methods for ion traps are described herein. One apparatus includes a number of microwave (MW) rails (110) and a number of radio frequency (RF) rails (108) formed with substantially parallel longitudinal axes and with substantially coplanar upper surfaces. The apparatus includes two sequences of direct current (DC) electrodes (106) with each sequence formed to extend substantially parallel to the substantially parallel longitudinal axes of the MW rails (110) and the RF rails (108). The apparatus further includes a number of through-silicon vias (TSVs) (115) formed through a substrate (105) of the ion trap (100) to provide an electrical potential to DC electrodes (106) and a trench capacitor (116) formed in the substrate (105) around at least one TSV (115).

公开(公告)号：EP3224860A1

公开(公告)日：2017-10-04

申请号：EP15862620.0

申请日：2015-11-24

申请人： Texas Instruments Incorporated

发明人： HU, Binghua ,  PENDHARKAR, Sameer P. ,  JACOBS, Jarvis Benjamin

IPC分类号： H01L21/762

CPC分类号： H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

摘要： A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

摘要翻译： 通过在深沟槽的侧壁上形成衬底中的深沟槽和电介质衬垫来形成半导体器件。 第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬里上的深沟槽中，但不填充深沟槽。 掺杂剂被注入到第一多晶硅层中。 在第一层多晶硅上形成第二层多晶硅。 热驱动退火激活和扩散掺杂剂。 在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。 在另一个版本中，深沟槽中的多晶硅通过电介质衬里与衬底隔离。

公开(公告)号：EP3050843A1

公开(公告)日：2016-08-03

申请号：EP15195480.7

申请日：2015-11-19

申请人： Honeywell International Inc.

发明人： YOUNGNER, Daniel

IPC分类号： B82Y10/00 ,  G06N99/00 ,  G21K1/00 ,  H01J49/00 ,  H01L29/94

CPC分类号： H01L29/945 ,  G21K1/00 ,  H01J49/0018

摘要： A Device (101, 201, 301) for ion trapping is described herein. One device (101, 201, 301) includes a through-silicon via (TSV) (302, 602) and a trench capacitor (304, 604) formed around the TSV (302, 602).

摘要翻译： 本文描述了用于离子捕获的装置（101,201,301）。 一个器件（101,201,301）包括穿过硅通孔（TSV）（302,602）和围绕TSV（302,602）形成的沟槽电容器（304,604）。

公开(公告)号：EP1979949B1

公开(公告)日：2014-09-24

申请号：EP07710011.3

申请日：2007-01-09

申请人： International Business Machines Corporation

发明人： CHENG, Kangguo ,  RASSEL, Robert, M.

IPC分类号： H01L29/94 ,  H01L21/334 ,  H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L21/02 ,  H01L27/01

CPC分类号： H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

公开(公告)号：EP2423947A3

公开(公告)日：2014-02-26

申请号：EP11169049.1

申请日：2011-06-08

申请人： Semiconductor Components Industries, LLC

发明人： Parsey, John Michael, Jr ,  Grivna, Gordon

IPC分类号： H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/20 ,  H01L28/91 ,  H01L29/6609 ,  H01L29/66106 ,  H01L29/861 ,  H01L29/866 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00

摘要： A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.

摘要翻译： 半导体衬底可以被图案化以限定沟槽和特征。 在一个实施例中，可以形成沟槽，使得在用材料填充沟槽之后，填充沟槽的底部部分可以在衬底变薄操作期间暴露。 在另一个实施例中，沟槽可以用热氧化物填充。 该特征可以具有减小在后续处理期间在特征和沟槽的壁之间的距离将被改变的可能性的形状。 结构可以至少部分地形成在沟槽内，其中通过利用沟槽的深度，结构可以具有相对大的面积。 该结构可用于制造电子部件，例如无源部件和贯穿基板通孔。 定义沟槽和形成结构的过程顺序可以针对许多不同的工艺流程进行定制。

公开(公告)号：EP2423947A2

公开(公告)日：2012-02-29

申请号：EP11169049.1

申请日：2011-06-08

申请人： Semiconductor Components Industries, LLC

发明人： Parsey, John Michael, Jr ,  Grivna, Gordon

IPC分类号： H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/20 ,  H01L28/91 ,  H01L29/6609 ,  H01L29/66106 ,  H01L29/861 ,  H01L29/866 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00

摘要： A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.

公开(公告)号：EP2306626A1

公开(公告)日：2011-04-06

申请号：EP09171834.6

申请日：2009-09-30

申请人： NXP B.V.

发明人： Villar Pique, Gerard ,  Warmerdam, Leo ,  Roozeboom, Freddy ,  Bergveld, Hendrik Johannes

IPC分类号： H02M3/07 ,  H01L21/02 ,  H01L29/94

CPC分类号： H02M3/07 ,  H01L29/66181 ,  H01L29/94 ,  H01L29/945 ,  H02M2003/072

摘要： Disclosed is a voltage conversion circuit (10) comprising a flying capacitor (12) formed in or on a semiconductor substrate (26), said flying capacitor having a first electrode selectively coupled to an input node for connecting the flying capacitor between different voltage levels (V bat ; V 2 ) and a second electrode selectively coupled to an output node (V out ), wherein at least one of the first electrode and the second electrode form a first region of a parasitic capacitance (110), the second region of which is formed by a part of the substrate (or any other conductor at constant voltage), the voltage conversion circuit further comprising a biasing element (80) for increasing the impedance of the conductive path between the first region and the second region, wherein the biasing element is selected from the group consisting of a bias voltage source, a bias resistor and a series-connected capacitor, which may be provided by an additional PN junction.

摘要翻译： 公开了一种电压转换电路（10），其包括形成在半导体衬底（26）中或其上的浮动电容器（12），所述浮动电容器具有选择性地耦合到输入节点的第一电极，用于在不同的电压电平之间连接所述快速电容器 V bat; V 2）和选择性地耦合到输出节点（V out）的第二电极，其中第一电极和第二电极中的至少一个形成寄生电容（110）的第一区域，其第二区域 由所述基板的一部分（或任何其它导体处于恒定电压）形成，所述电压转换电路还包括用于增加所述第一区域和所述第二区域之间的导电路径的阻抗的偏置元件（80），其中所述偏置 元件选自由偏置电压源，偏置电阻器和串联电容器组成的组，其可以由附加的PN结提供。

公开(公告)号：EP2255376A1

公开(公告)日：2010-12-01

申请号：EP09712370.7

申请日：2009-02-17

申请人： NXP B.V.

发明人： NEUILLY, Francois ,  LE CORNEC, Francois

IPC分类号： H01L21/02 ,  H01L23/498 ,  H01L27/06 ,  H01L21/334 ,  H01L27/08 ,  H01L29/94 ,  H01L21/768 ,  H01L27/02

CPC分类号： H01L27/0805 ,  H01L23/49827 ,  H01L27/0207 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940).Via connections (920) are provided in trenches that go through the whole thickness of the wafer.