公开(公告)号：EP0583872B1

公开(公告)日：1997-10-29

申请号：EP93305040.3

申请日：1993-06-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, OM P. ,  Llgenstein, Kerry A.

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/17716

公开(公告)号：EP0746105A3

公开(公告)日：1997-09-03

申请号：EP96480059.3

申请日：1996-05-07

申请人： International Business Machines Corporation

发明人： Furtek, Frederick Curtis ,  Keyser III, Frank Ray ,  Gould, Scott Whitney ,  Worth, Brian A. ,  Zittritsch, Terrance John

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

公开(公告)号：EP0780017A1

公开(公告)日：1997-06-25

申请号：EP96923615.0

申请日：1996-07-10

申请人： Xilinx, Inc.

发明人： LEEDS, Kenneth, E. ,  ERICKSON, Charles, R.

IPC分类号： G11C11 ,  G11C7 ,  G11C8 ,  G11C16 ,  H03K19

CPC分类号： H03K19/17776 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  H03K19/17704 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/17772

摘要： A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ('FPGA'). The memory device can provide the configuration data on a serial output lead or a parallel data bus.

公开(公告)号：EP0746105A2

公开(公告)日：1996-12-04

申请号：EP96480059.3

申请日：1996-05-07

申请人： International Business Machines Corporation

发明人： Furtek, Frederick Curtis ,  Keyser III, Frank Ray ,  Gould, Scott Whitney ,  Worth, Brian A. ,  Zittritsch, Terrance John

IPC分类号： H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

摘要翻译： 公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。 该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。 每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。 在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。 时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。 时钟门电路与每个逻辑单元中的输出多路复用器协同控制。 网络被设计为具有最小化信号偏移的特征，包括信号源缓冲，多路复用器信号缓冲以及作为信号传播距离的函数的输出驱动器尺寸。

公开(公告)号：EP0746103A2

公开(公告)日：1996-12-04

申请号：EP96112929.3

申请日：1993-04-07

申请人： ALTERA CORPORATION

发明人： Cliff, Richard G. ,  Lytle, Craig Schilling ,  Ahanin, Bahram ,  Heile, Francis B. ,  Pedersen, Bruce B. ,  Veenstra, Kerry

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

公开(公告)号：EP0746102A2

公开(公告)日：1996-12-04

申请号：EP96112928.5

申请日：1993-04-07

申请人： ALTERA CORPORATION

发明人： Cliff, Richard G. ,  Lytle, Craig Schilling ,  Ahanin, Bahram ,  Heile, Francis B. ,  Pedersen, Bruce B. ,  Veenstra, Kerry

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，这些模块在多个逻辑阵列块（“LAB”）中被组合在一起。 LAB以二维阵列排列在电路上。 提供导体网络用于将任何逻辑模块与任何其他逻辑模块互连。 另外，相邻或附近的逻辑模块可以彼此连接，以便用于例如在逻辑模块之间提供进位链和/或用于将两个或更多个模块连接在一起以提供更复杂的逻辑功能，而不必使用通用互连 网络。 提供另一种所谓的快速或通用导体网络，用于在整个电路中分配广泛使用的逻辑信号，例如时钟信号和清除信号。

公开(公告)号：EP0512536A3

公开(公告)日：1995-08-02

申请号：EP92107697.2

申请日：1992-05-07

申请人： KABUSHIKI KAISHA TOSHIBA ,  PILKINGTON MICRO-ELECTRONICS LIMITED

发明人： Saeki, Yukihiro, c/o Intellectual Property Div. ,  Muroga, Hiroki, c/o Intellectual Property Div. ,  Shigematsu, Tomohisa c/o Intellectual Property Div ,  Hibi, Toshio, c/o Intellectual Property Div. ,  Kawahara, Yasuo, c/o Intellectual Property Div. ,  Maru, Kazunao, c/o Intellectual Property Div. ,  Austin, Kenneth ,  Work, Gordon Stirling ,  Wedgwood, Darren Martin

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  G11C11/404 ,  G11C11/412 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).

公开(公告)号：EP0340891B1

公开(公告)日：1994-11-02

申请号：EP89301781.4

申请日：1989-02-23

申请人： ALTERA CORPORATION

发明人： Norman, Kevin Alan ,  Frankovich, Robert J.

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

公开(公告)号：EP0513983A1

公开(公告)日：1992-11-19

申请号：EP92302773.4

申请日：1992-03-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Ilgenstein, Kerry A. ,  Landers, George ,  Moench, Jerry ,  Schmitz, Nicholas A.

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品术语阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语阵列引导到选定的逻辑宏单元，使得没有产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可路由因素。 第二系列PLD具有比第一系列PLD更大的引脚与逻辑比。

公开(公告)号：EP0340891A2

公开(公告)日：1989-11-08

申请号：EP89301781.4

申请日：1989-02-23

申请人： ALTERA CORPORATION

发明人： Norman, Kevin Alan ,  Frankovich, Robert J.

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic device having a relatively small number of programmable product terms (0E,SETN,INV,P0,P1,P2,ACLK,CLEARN) ("P-terms") feeding each fixed combinatorial logic device (51), and additional "expander" programmable P-terms (EXP1,EXP2) which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In order to conserve word lines in the programmable array, multi­plexers (150) allow selection of whether expander outputs or external inputs (44) will be applied to certain word lines (102).

摘要翻译： 一种可编程逻辑器件，其具有相对较少数量的可编程产品项（0E，SETN，INV，P0，P1，P2，ACLK，CLEARN）（“P项”），馈送每个固定的组合逻辑器件（51） 扩展器“可编程P项（EXP1，EXP2），不直接馈送固定设备。 可以通过对馈送固定设备的P项进行适当编程来执行相对简单的逻辑功能。 可以通过适当地编程所需数量的扩展器P-项来执行更复杂的逻辑功能，然后通过另一个P项组合这些P项的输出。 为了节省可编程阵列中的字线，多路复用器（150）允许选择扩展器输出或外部输入（44）是否将被施加到某些字线（102）。