公开(公告)号：EP0740338A3

公开(公告)日：1998-01-07

申请号：EP96108241.9

申请日：1991-07-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Nakagawa, Akio ,  Ogura, Tsuneo

IPC分类号： H01L21/762 ,  H01L21/8228

CPC分类号： H01L29/7317 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/7436 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A composite integrated circuit device includes a semiconductor element chip (1), a positioning guide (3) formed on the semiconductor element chip (1), and an electronic element (4) set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide (3) and mounted thereon.

摘要翻译： 一种复合集成电路装置，包括半导体元件芯片（1），形成在所述半导体元件芯片（1）上的定位引导件（3）和设置在所述半导体元件芯片上的预设位置中的电子元件（4） 通过定位导向件（3）对准并安装在其上。

公开(公告)号：EP0762492A1

公开(公告)日：1997-03-12

申请号：EP96401812.1

申请日：1996-08-23

申请人： SONY CORPORATION

发明人： Anmo, Hiroaki ,  Kanematsu, Shigeru ,  Gomi, Takayuki

IPC分类号： H01L21/74 ,  H01L21/8228 ,  H01L21/266

CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L21/8228 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975 ,  H01L2924/00

摘要： To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor (1) it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening (13) [alignment mark (16)] and a second opening (14) are formed in an insulating film (12) formed on a semiconductor base (11) and a doping mask (15) is then formed on the semiconductor base (11), a third opening (17) is formed thereon with the alignment mark (16) as a reference. After an impurity (18) is introduced into the semiconductor base (11) through the third opening (17), the doping mask (15) is removed and after that an impurity (19) is introduced into the semiconductor base (11) by solid-phase diffusion through the second opening (14) and a first embedded diffusion layer (20) is thereby formed and at the same time the impurity (18) is caused to diffuse and form a second embedded diffusion layer (21). Then, after an epitaxial layer is formed, an impurity diffusion layer is formed therein by ion injection (not shown).

摘要翻译： 例如，为了形成NPN和PNP晶体管以形成互补双极型晶体管（1），必须使外延层成为厚膜，导致NPN晶体管的特性劣化。 此外，由于需要形成对准标记的步骤，这增加了制造互补双极晶体管所需的制造步骤的数量。 本发明提供了如下解决该问题的半导体器件制造方法：在形成在半导体基底上的绝缘膜（12）中形成第一开口（13）对准标记（16）和第二开口（14）之后， 11），然后在半导体基底（11）上形成掺杂掩模（15），在其上形成有以对准标记（16）为基准的第三开口（17）。 在通过第三开口（17）将杂质（18）引入半导体基底（11）之后，去除掺杂掩模（15），然后通过固体将杂质（19）引入半导体基底（11） 由此形成通过第二开口（14）和第一嵌入扩散层（20）的相扩散，并且同时使杂质（18）扩散并形成第二嵌入扩散层（21）。 然后，在形成外延层之后，通过离子注入形成杂质扩散层（未示出）。

公开(公告)号：EP0721221A2

公开(公告)日：1996-07-10

申请号：EP95119364.8

申请日：1995-12-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ning, Tak Hung ,  Wu, Ben Song

IPC分类号： H01L29/423 ,  H01L29/732 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8228 ,  H01L21/8249

CPC分类号： H01L29/66265 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/78642

摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

摘要翻译： 一种用于在绝缘体（SOI）技术中制造超大规模集成（ULSI）电路的工艺，其中可以是双极型，场效应晶体管或组合的器件结构形成在其下面和后面具有绝缘的垂直硅侧壁中 以便创建SKI设备结构。 当制造时，硅侧壁器件SOI结构采取单元的形式，每个单元具有多个双极器件，FET器件或这些器件的组合，诸如集电极，发射极，基极，源极，漏极和栅极 在单元中的器件的区域的平面内互连并且可以在相邻单元中的器件的区域的平面内互连。 此外，可以从硅侧壁的背面形成与相邻单元的互连。

公开(公告)号：EP0519592A2

公开(公告)日：1992-12-23

申请号：EP92303984.6

申请日：1992-05-01

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Ramde, Amolak R.

IPC分类号： H01L21/8228 ,  H01L21/761

CPC分类号： H01L21/82285 ,  H01L21/761 ,  H01L21/76202 ,  Y10S148/01

摘要： A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

摘要翻译： 一种用于创建自对准垂直排列的平面型晶体管的过程。 的优选实施方案涉及排列在常规整体式的，外延，PN结隔离，集成电路垂直平面的两个NPN和PNP晶体管的同时制造。 场氧化采用表面隔离的装置和协助自对准的改善。