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96 条记录 (耗时 0.017 秒)

    A phase estimator
    61.
    发明公开
    A phase estimator 审中-公开
    Phasenschätzer

    公开(公告)号：EP2890070A1

    公开(公告)日：2015-07-01

    申请号：EP13199552.4

    申请日：2013-12-24

    申请人： NXP B.V.

    发明人： Drago, Salvatore

    IPC分类号： H04L27/38

    CPC分类号： H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/804 ,  H04L27/3818

    摘要： A phase estimator comprising a first input terminal configured to receive a first analogue input signal; a second input terminal configured to receive a second analogue input signal, wherein the second analogue input signal is 90° out of phase with the first analogue input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analogue input signal and the second analogue input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.

    摘要翻译： 相位估计器，包括被配置为接收第一模拟输入信号的第一输入端; 第二输入端子，被配置为接收第二模拟输入信号，其中所述第二模拟输入信号与所述第一模拟输入信号相差90°。 相位估计器被配置为提供表示第一模拟输入信号和第二模拟输入信号的相位的数字字。 相位估计器包括被配置为存储N位作为数字字的寄存器，第一参考信号发生器，第二参考信号发生器和比较器。

    CMOS TRANSISTOR LINEARIZATION METHOD
    62.
    发明公开
    CMOS TRANSISTOR LINEARIZATION METHOD 审中-公开
    线性化程序对CMOS晶体管

    公开(公告)号：EP2853031A1

    公开(公告)日：2015-04-01

    申请号：EP13793375.0

    申请日：2013-05-08

    申请人： Analog Devices, Inc.

    发明人： HENSLEY, Joseph M. ,  MURDEN, Franklin M.

    IPC分类号： H03M1/34

    CPC分类号： H03K17/687 ,  H03M1/06 ,  H03M1/1245 ,  H03M1/38

    摘要： A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

    Digital correction for missing codes caused by capacitive mismatching in successive approximation analog-to-digital converters
    65.
    发明公开
    Digital correction for missing codes caused by capacitive mismatching in successive approximation analog-to-digital converters 失效
    数字校正缺失引起的渐进Annährungs/ AD电容失配的代码。

    公开(公告)号：EP0658981A1

    公开(公告)日：1995-06-21

    申请号：EP93830503.4

    申请日：1993-12-15

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Moroni,Angelo

    IPC分类号： H03M1/38 ,  H03M1/06

    CPC分类号： H03M1/0612 ,  H03M1/38

    摘要： An ADC, comprising an internal DAC, driven by a successive approximation SAR, and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, permits to correct incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost-effective and permits to greatly improve production yield of complex devices containing ADCs.

    摘要翻译： 在ADC，DAC内部的包括，由逐次逼近SAR，和比较器驱动时，控制设置有校正逻辑电路做了验证在每个转换例程的结束执行和校正例程。 主 - 从细胞那样构成SAR设置有专用电路，响应所述校正控制电路，用于通过至少在LSB确认，递增或递减存储在单元中的位。 一个非常简单的程序，在每个转换周期结束时进行的，允许以纠正错误地转换因为在内部DAC失码的出现的数字数据。 校正器不要求使用的存储器和/或模拟电路，是非常经济有效的，并且允许大大提高包含ADC的复杂器件的生产成品率。

    Circuit soustracteur-amplificateur pour convertisseur analogique numérique à cascade
    66.
    发明公开
    Circuit soustracteur-amplificateur pour convertisseur analogique numérique à cascade 失效
    减法放大器电路，用于级联模拟 - 数字转换器。

    公开(公告)号：EP0376828A1

    公开(公告)日：1990-07-04

    申请号：EP89403627.6

    申请日：1989-12-22

    申请人： THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

    发明人： Tung, Pham Ngu

    IPC分类号： H03M1/14 ,  H03M1/16

    CPC分类号： H03M1/12 ,  H03M1/145 ,  H03M1/168 ,  H03M1/38 ,  H03M1/808

    摘要： Dans un convertisseur analogique-numérique (CAN) à cascade, un premier CAN (1) détermine les bits de poids supérieurs. Pour déterminer les bits de poids inférieurs, dans un deuxième CAN (4), il faut faire la différence entre le signal analogique d'entrée (V E ) et sa partie déjà numérisée, reconvertie en analogique.
    Le soustracteur-amplificateur reçoit d'une part le signal d'entrée (V E ), qui est transformé en un courant (i E ), et d'autre part les bits de poids supérieurs (S₄ à S₇) sur un convertisseur numérique-analogique. Ceci constitue une source modulable qui fournit un courant (i c ). Deux transistors en parallèle (E et A) font la différenciation entre le courant de la source modulable (i c ) et le courant (i E ) correspondant au signal d'entrée (V E ) et l'amplifient.
    Application aux CAN à cascade.

    Method and apparatus for converting radiant energy levels to digital data
    68.
    发明公开
    Method and apparatus for converting radiant energy levels to digital data 失效
    将辐射能级转换为数字数据的方法和装置

    公开(公告)号：EP0125417A3

    公开(公告)日：1988-05-04

    申请号：EP84102703

    申请日：1984-03-13

    申请人： MILES LABORATORIES, INC.

    发明人： White, James A.

    IPC分类号： H03K13/17

    CPC分类号： G01J1/42 ,  H03M1/38

    摘要： A method and apparatus for converting radiant energy levels to digital data wherein an image sensor is provided having at least one row of sensor elements each including a light sensitive capacitor and an access switch and which changes state and produces a corresponding binary output signal when a predetermined charge threshold is exceeded by the capacitor whose charge is a function of intensity and period of an illumination. The row of elements is first calibrated by illuminating same with a reference light source and sensing at a first frequency (F) such that approximately one half of the elements change state and counting the digital output signals corresponding to the changes of state to obtain a first number (B). Thereafter, the row is illuminated with an unknown light source which has a lower radiant energy level than that of the reference light source and senses at a frequency F/2. The digital output signals corresponding to the changes of state are counted to obtain a second number (A). The numbers A and B are compared to produce a digital "1" signal when A > B and a digital "0" when A 1 . The sensing and comparing are repeated for each successive bit N 2 , N 3 ...N k of a K bits of digital data at successive sensing frequencies in accordance with