公开(公告)号：EP2345035A1

公开(公告)日：2011-07-20

申请号：EP09820146.0

申请日：2009-10-14

申请人： MOSAID Technologies Incorporated

发明人： KIM, Jin-Ki ,  PYEON, Hong, Beom

IPC分类号： G11C7/10 ,  G11C16/06 ,  G11C5/06 ,  G11C7/22

CPC分类号： G11C7/00 ,  G11C5/02 ,  G11C5/025

摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

公开(公告)号：EP2299653A1

公开(公告)日：2011-03-23

申请号：EP10184867.9

申请日：2001-12-21

申请人： Mosaid Technologies Incorporated

发明人： Low, Arthur, John ,  Davis, Stephen, J.

IPC分类号： H04L29/06 ,  H04L29/08 ,  H04L12/56

CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

摘要： There is disclosed a data processing system, comprising: a plurality of data processors (102) configured to perform functions of processing data packets; a server processor (100) configured to generate control data including a list of at least one function to be performed on a received data packet; and a controller in communication with the server processor and configured to process the control data, the controller being responsive to the control data to: select from the plurality of data processors at least one data processor configured to perform the at least one function; and cause the at least one selected data processor to perform the at least one function on the data packet based on the control data.

摘要翻译： 公开了一种数据处理系统，包括：多个数据处理器（102），被配置为执行处理数据分组的功能; 服务器处理器（100），被配置为生成包括要对接收的数据分组执行的至少一个功能的列表的控制数据; 以及与所述服务器处理器通信并被配置为处理所述控制数据的控制器，所述控制器响应于所述控制数据来从所述多个数据处理器中选择被配置为执行所述至少一个功能的至少一个数据处理器; 并且使所述至少一个所选择的数据处理器基于所述控制数据对所述数据分组执行所述至少一个功能。

公开(公告)号：EP2276033A1

公开(公告)日：2011-01-19

申请号：EP10175918.1

申请日：2001-06-29

申请人： Mosaid Technologies Incorporated

发明人： Demone, Paul

IPC分类号： G11C7/22 ,  G11C11/4076

CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

摘要： A Dynamic Random Access Memory (DRAM) performs, read, write, and refresh operations. The DRAM includes a plurality of sub-arrays (504), each having a plurality of memory cells (604), each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device (911) for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit (908,910,912) is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse (WTPi). The read, write, and refresh operation are performed in the same amount of time.

摘要翻译： 动态随机存取存储器（DRAM）执行，读取，写入和刷新操作。 DRAM包括多个子阵列（504），每个子阵列具有多个存储单元（604），每个存储单元与互补位线对和字线耦合。 DRAM还包括用于断言所选择的一条字线的字线使能装置（911）和用于断言所选位线对之一的列选择装置。 提供定时电路（908,910,912），用于响应于字线定时脉冲（WTPi）来控制字线使能装置，列选择装置以及读，写和刷新操作。 读取，写入和刷新操作在相同的时间量内执行。

公开(公告)号：EP2270811A1

公开(公告)日：2011-01-05

申请号：EP10075650.1

申请日：2001-07-06

申请人： MOSAID Technologies Incorporated

发明人： Demone, Paul W

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/4076

CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/002 ,  G11C2207/2281

摘要： A semiconductor memory device comprises a plurality of memory cells; a plurality of bit and word lines; a plurality of sense amplifiers for sensing and amplifying signals from the bit lines; a plurality of column access devices for coupling the bit lines to a data line of the memory device; delay circuitry for providing a delayed word line timing pulse and a further delayed word line timing pulse; and enable circuitry for enabling the sense amplifier in response to the delayed word line timing pulse and the column access device in response to the further delayed word line timing pulse.

摘要翻译： 半导体存储器件包括多个存储单元; 多个位和字线; 用于感测和放大来自位线的信号的多个读出放大器; 多个列存取装置，用于将位线耦合到存储装置的数据线; 延迟电路，用于提供延迟的字线定时脉冲和另外延迟的字线定时脉冲; 以及响应于进一步延迟的字线定时脉冲，响应于延迟的字线定时脉冲和列存取装置使能读出放大器的使能电路。

公开(公告)号：EP2264948A1

公开(公告)日：2010-12-22

申请号：EP10176156.7

申请日：2000-07-03

申请人： Mosaid Technologies Incorporated

发明人： Binder, Yehuda

IPC分类号： H04L12/40 ,  H04L12/42

CPC分类号： H04L41/0836 ,  G05B2219/21039 ,  G05B2219/25181 ,  H04L12/40 ,  H04L12/40019 ,  H04L12/403 ,  H04L12/42 ,  H04L12/66 ,  H04L49/40

摘要： A device for carrying a power signal and a serial digital data signal over a cable comprises a connector for connecting to the cable; a splitter having first, second and third ports, the splitter being configured so that the power signal is passed from the first port to the second port, and the digital data signal is passed between the first and third ports; a transceiver coupled to the third port of the splitter for point-to-point communication of the full duplex serial digital data signal over the cable; a power supply for voltage conversion coupled to and powered from the second port of the splitter, the power supply having a power source port connected to the transceiver for powering the transceiver from the power supply; a data port coupled to the transceiver and connectable to a data unit for connecting the digital data signal to the data unit; and an indicator powered by the power supply for indicating a status of the device status.

摘要翻译： 通过电缆传输电源信号和串行数字数据信号的设备包括用于连接到电缆的连接器; 具有第一，第二和第三端口的分配器，分配器被配置为使得功率信号从第一端口传递到第二端口，并且数字数据信号在第一和第三端口之间传递; 耦合到分离器的第三端口的收发器，用于通过电缆进行全双工串行数字数据信号的点对点通信; 用于电压转换的电源，其耦合到所述分离器的所述第二端口并由所述第二端口供电，所述电源具有连接到所述收发器的电源端口，用于从所述电源向所述收发器供电; 耦合到收发器并可连接到数据单元以将数字数据信号连接到数据单元的数据端口; 以及由电源供电的指示器，用于指示设备状态的状态。

公开(公告)号：EP2251980A1

公开(公告)日：2010-11-17

申请号：EP10171395.6

申请日：2003-12-29

申请人： Mosaid Technologies Incorporated

发明人： Vlasenko, Peter ,  Haerle, Dieter

IPC分类号： H03L7/087

CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

摘要： There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment.

摘要翻译： 公开了一种延迟锁定环路（300），包括：数字延迟电路（302），其使数字延迟元件（400）能够在延迟锁定环路（300）中的初始化期间提供粗略的相位调整; 计数器（308），被配置为控制启用的数字延迟元件（400）的数量; 以及模拟延迟电路（304），其在粗略的相位调整完成​​之后在延迟锁定环路（300）中提供精细的相位调整，并且其中模拟延迟电路（304）在精细相位调整期间采用可变控制信号 。

公开(公告)号：EP2251872A1

公开(公告)日：2010-11-17

申请号：EP09001914.2

申请日：2009-02-11

申请人： Mosaid Technologies Incorporated

发明人： Pyeon, Hong Beom

IPC分类号： G11C5/00 ,  G11C7/22 ,  G11C8/12 ,  G06F13/16

CPC分类号： G11C5/00 ,  G06F12/06 ,  G06F13/1684 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C7/22 ,  G11C8/12

摘要： A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.

摘要翻译： 一种用于将命令选择性地广播到与存储器控制器串联连接的多个设备的子集的方法和系统，其中多个设备中的每一个具有唯一的标识号（ID）。 存储器控制器指定要执行命令的设备的子集，排除未被选择的设备执行命令。 存储器控制器将指定设备的ID号编码为单个编码地址，并将该命令与编码地址一起发送到串联连接的设备。 每个设备以串行比特流接收分组，并使用其ID号对编码的地址进行解码，以便确定是否被选择。 如果选择了该设备，则执行该命令。 否则，不执行命令就转发报文。

公开(公告)号：EP2002442B1

公开(公告)日：2010-11-10

申请号：EP07719433.0

申请日：2007-03-29

申请人： Mosaid Technologies Incorporated

发明人： KIM, Jin-Ki

IPC分类号： G11C7/10 ,  G11C11/4193 ,  G11C16/00

CPC分类号： G11C7/1042 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C7/1021 ,  G11C16/10 ,  G11C16/32 ,  G11C2216/22 ,  G11C2216/24

摘要： A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

摘要翻译： 一种闪存系统架构，具有串行连接的闪存设备以实现数据的高速编程。 数据的高速编程通过在系统中的存储器设备之间交错要编程的数据的页面来实现，使得不同页面的数据被存储在不同的存储器设备中。 内存控制器为每个内存设备发出程序命令。 当每个存储器设备接收到程序命令时，它开始编程操作或将命令传递给下一个存储器设备。 因此，闪存系统中的存储器件依次编程数据页，从而最小化将每页数据编程到闪存系统中的延迟。 存储器控制器可以执行损耗均衡算法以使每个存储器设备的耐久性最大化，或者为任何尺寸的数据优化编程性能和耐久性。

公开(公告)号：EP1588489B1

公开(公告)日：2010-09-01

申请号：EP03785447.8

申请日：2003-12-29

申请人： Mosaid Technologies Incorporated

发明人： VLASENKO, Peter ,  HAERLE, Dieter

IPC分类号： H03L7/087

CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

摘要： There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment.

公开(公告)号：EP2220653A1

公开(公告)日：2010-08-25

申请号：EP08865169.0

申请日：2008-12-19

申请人： MOSAID Technologies Incorporated

发明人： PYEON, Hong Beom ,  KIM, Jin-Ki

IPC分类号： G11C16/30

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.