公开(公告)号：EP0568439B1

公开(公告)日：1994-12-14

申请号：EP93401085.1

申请日：1993-04-27

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Rouy, Olivier, Cabinet BALLOT-SCHMIT

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5006

公开(公告)号：EP0568439A1

公开(公告)日：1993-11-03

申请号：EP93401085.1

申请日：1993-04-27

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Rouy, Olivier, Cabinet BALLOT-SCHMIT

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5006

Abstract: L'invention concerne un circuit de détection de fuites de courant sur une ligne de bit d'une mémoire morte électriquement programmable.
Il comprend essentiellement un générateur de courant 2 et un moyen 8 pour appliquer zéro volts sur la grille de toutes les cellules de la ligne de bit. L'information de détection est délivrée par un circuit de comparaison 1. Elle correspond au résultat de la comparaison entre le courant de test et le courant circulant sur la ligne de bit. Avantageusement le circuit de détection est incorporé au circuit de lecture de la mémoire.
L'invention concerne aussi la méthode de détection associée et un circuit mémoire comprenant un tel circuit de détection.

Abstract translation: 本发明涉及一种用于检测电可编程只读存储器的位线中的电流泄漏的电路。 它基本上包括电流发生器2和用于将零电压施加到位线的所有单元的栅格的装置8。 检测信息由比较电路1传送。它对应于测试电流与流过位线的电流之间的比较结果。 有利地，检测电路并入存储器读出电路中。 本发明还涉及相关的检测方法和包括这种检测电路的存储电路。

公开(公告)号：EP0318363B1

公开(公告)日：1992-07-08

申请号：EP88402905.9

申请日：1988-11-18

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Devin, Jean

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C2029/5006

公开(公告)号：EP0146975A2

公开(公告)日：1985-07-03

申请号：EP84200830.2

申请日：1984-06-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Chan, Albert ,  Fitzpatrick Mark ,  Bosnyak, Robert J. ,  Tsui, Cyrus ,  Goddard, Don

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5006

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

公开(公告)号：EP2973569A4

公开(公告)日：2017-04-12

申请号：EP13877463

申请日：2013-03-15

Applicant: SILICON STORAGE TECH INC

Inventor： PI XIAO YAN ,  QIAN XIAOZHOU ,  YUE KAIMAN ,  ZHOU YAO ,  ZHU YAOHUA

IPC: G11C7/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

Abstract translation: 公开了一种改进的感测电路，其利用未使用的存储器阵列中的位线来提供与另一存储器阵列中的选定单元进行比较的参考值。 公开了一种可以进行自检以识别位线的泄漏电流约为可接受阈值的电路。

公开(公告)号：EP2973569A1

公开(公告)日：2016-01-20

申请号：EP13877463.3

申请日：2013-03-15

Applicant: Silicon Storage Technology Inc.

Inventor： PI, Xiao Yan ,  QIAN, Xiaozhou ,  YUE, Kaiman ,  ZHOU, Yao ,  ZHU, Yaohua

IPC: G11C7/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

公开(公告)号：EP2591473A1

公开(公告)日：2013-05-15

申请号：EP11730162.2

申请日：2011-06-29

Applicant: SanDisk Technologies Inc.

Inventor： LI, Yan ,  LEE, Dana ,  HUYNH, Jonathan H. ,  PAN, Feng ,  POPURI, Viswakiran ,  CAZZANIGA, Marco

IPC: G11C29/02

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5006

Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

公开(公告)号：EP1606824A1

公开(公告)日：2005-12-21

申请号：EP04716681.4

申请日：2004-03-03

Applicant: Koninklijke Philips Electronics N.V.

Inventor： PINEDA DE GYVEZ, Jose, D., J. ,  SACHDEV, Manoj ,  PAVLOV, Andrei

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/5006

Abstract: A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as 'weak' (step 114).

公开(公告)号：EP1560223A3

公开(公告)日：2005-09-07

申请号：EP04017679.4

申请日：2004-07-26

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Perner, Frederick A. ,  Bhattacharyya, Manoj K.

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A magnetic memory cell write current threshold detector [510]. The magnetic memory cell write current threshold detector [510] includes a first MRAM test cell [512] receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell [514] receiving the write current and sensing when the write current exceeds a second threshold.

公开(公告)号：EP1361450B1

公开(公告)日：2004-12-29

申请号：EP02010478.2

申请日：2002-05-08

Applicant: Infineon Technologies AG

Inventor： Chee Hong, Liau, Eric

IPC: G01R31/30 ,  G11C29/00

CPC classification number: G11C29/56004 ,  G01R31/3004 ,  G11C29/50 ,  G11C29/56 ,  G11C2029/5006