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公开(公告)号：EP0281740A3
公开(公告)日：1990-05-09
申请号：EP88100944.3
申请日：1988-01-22
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/076 , G06F11/1052 , G11C29/02 , G11C29/10 , G11C29/18
摘要： A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.
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公开(公告)号：EP0359372A2
公开(公告)日：1990-03-21
申请号：EP89307291.8
申请日：1989-07-19
发明人： Bruce, William , Smelser, Donald W.
摘要： A DRAM test system includes a storage location tester and controller tester. The storage location tester utilizes an error correction code which generates redundancy symbols corresponding to inverted data that are the binary inverse or compliment of the redundancy symbols corresponding to the non-inverted data. Thus each bit-location of an addressable storage location, consisting of both data and ECC redundancy bit locations, can be fully tested for storage and retrieval of both a ONE and a ZERO in only three read/write cycles. The controller tester tests the DRAM controller circuitry by sequencing it through various operations, at least one of which is a refresh operation. When a refresh operation occurs the node signals corresponding to the refresh operation are incorporated into a DRAM controller signature vector. To counter the effects of the refresh operation on the signature vector, a refresh-vector is applied to the signature vector register during the refresh operation and the contents of the register are updated. This results in the contents of the signature vector being "returned" to the pre-refresh contents at the end of a properly executed refresh. At the completion of the testing cycle the signature vector may then be compared with the expected output vector, which does not include any refresh operation information, to determine if the DRAM is functioning properly.
摘要翻译： DRAM测试系统包括存储位置测试仪和控制器测试仪。 存储位置测试器使用纠错码，该纠错码产生对应于对应于非反相数据的冗余符号的二进制逆或补码的反转数据的冗余符号。 因此，只有三个读/写周期，可以对包含数据和ECC冗余位位置的可寻址存储位置的每个位位置进行完全测试，以存储和检索ONE和ZERO。 控制器测试器通过各种操作对其进行排序来测试DRAM控制器电路，其中至少一个是刷新操作。 当刷新操作发生时，对应于刷新操作的节点信号被并入到DRAM控制器签名向量中。 为了对刷新操作对签名向量的影响，在刷新操作期间将刷新向量应用于签名向量寄存器，并且更新寄存器的内容。 这导致签名向量的内容在正确执行的刷新结束时被“返回”到预刷新内容。 在完成测试周期后，可以将签名矢量与不包括任何刷新操作信息的预期输出向量进行比较，以确定DRAM是否正常工作。
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公开(公告)号：EP0268289A3
公开(公告)日：1989-11-08
申请号：EP87117063.5
申请日：1987-11-19
申请人： NEC CORPORATION
CPC分类号： G06F11/2215 , G06F11/1008 , G06F11/1076 , G11C29/02 , G11C29/36
摘要： For sufficient diagnostic operation, there is disclosed a semiconductor memory device having a write-in mode, a read-out mode and a diagnostic mode, comprising;
a) a check-bit producing circuit (52) operative to produce check-bits based on data bits of a data information supplied from the outside thereof in the write-in mode; b) a plurality of memory cell groups (53) each capable of storing the data bits of the data information and the check bits produced by the check-bit producing circuit; c) an error detecting circuit (56) operative to identify at least one error bit opposite in logic level from the corresponding data bit on the basis of the data information stored in the memory cell group and to produce an output signal consisting of a plurality of data bits and representing the error bit, if any, in the read-out mode or the diagnostic mode; d) an error correction circuit (57) supplied with the data bits of the data information stored in the memory cell group and the output signal produced by the error detecting circuit and operative to change the error data bit to the correct data bit in the read-out mode or the diagnostic mode; and e) a test pattern producing circuit (60) operative to produce dummy bits having an error data bit and check bits produced on the basis of data bits without the error data bit and supplying the dummy bits to the error detecting circuit in the diagnostic mode.摘要翻译： 为了充分的诊断操作，公开了一种具有写入模式，读出模式和诊断模式的半导体存储器件，包括： a）校验位产生电路（52），用于在写入模式中基于从其外部提供的数据信息的数据位产生校验位; b）多个存储单元组（53），每个存储单元组能够存储数据信息的数据位和校验位产生电路产生的校验位; c）一个错误检测电路（56），用于根据存储在存储单元组中的数据信息，识别逻辑电平与相应数据位相反的至少一个错误位，并产生一个由多个 数据位并在读出模式或诊断模式下表示错误位，如果有的话; d）提供有存储在存储单元组中的数据信息的数据位和由错误检测电路产生的输出信号的错误校正电路（57），用于将错误数据位改变为读取中的正确数据位 输出模式或诊断模式; 和e）一个测试模式产生电路（60），用于产生具有误差数据比特的伪比特和基于数据比特产生的校验比特而不用误差数据比特，并且在诊断模式下将伪比特提供给误差检测电路 。
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公开(公告)号：EP0188013B1
公开(公告)日：1989-11-08
申请号：EP85200827.5
申请日：1985-05-22
发明人： Bosnyak, Robert J.
CPC分类号： G11C29/02
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公开(公告)号：EP0195839B1
公开(公告)日：1989-08-09
申请号：EP85103736.6
申请日：1985-03-29
发明人： Andrusch, Georg , Baisch, Joachim , Barsuhn, Horst, Dipl.-Ing. , Wernicke, Friedrich C., Dipl.-Ing. , Wiedmann, Siegfried K., Dr. Dipl.-Ing.
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C11/41 , G11C29/02 , G11C29/50 , G11C29/50016
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76.发明公开Semiconductor memory device with protection cells 失效Halbleiter-Speichereinrichtung mit Schutzzellen。
公开(公告)号：EP0281868A2
公开(公告)日：1988-09-14
申请号：EP88102848.4
申请日：1988-02-25
申请人： NEC CORPORATION
IPC分类号： G11C7/00
摘要： For preventing sense amplifier circuits associated with memory cells from misjudgment, there is proposed a semiconductor memory device comprising protection cells (42 and 43) formed between memory cell array (1) and peripheral circuits (21 and 28), and the protection cells are coupled to an additional bit line pair (44) precharged to a predetermined voltage level approximately equal to those of bit line pairs (13 and 14) coupled to the memory cells, so that no difference voltage takes place between the additional bit line pair and the neighboring bit line pair, thereby eliminating a difference in characteristics of the sense amplifier circuits (7, 8 and 48) coupled thereto.
摘要翻译： 为了防止与存储器单元相关联的读出放大器电路误判，提出了一种半导体存储器件，包括形成在存储单元阵列（1）和外围电路（21和28）之间的保护单元（42和43），并且保护单元耦合 到预先充电到预定电压电平的额外位线对（44），其大约等于耦合到存储器单元的位线对（13和14）的预定电压电平，使得在附加位线对和相邻的位线对之间不发生差分电压 位线对，从而消除与其耦合的读出放大器电路（7,8和48）的特性差异。
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77.发明公开Apparatus and method for testing and verifying the refresh logic of dynamic MOS memories 失效用于测试和验证动态MOS存储器的刷新逻辑的装置和方法
公开(公告)号：EP0130534A3
公开(公告)日：1988-01-07
申请号：EP84107328
申请日：1984-06-26
IPC分类号： G11C29/00
CPC分类号： G11C29/02
摘要： The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.
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公开(公告)号：EP0198935A1
公开(公告)日：1986-10-29
申请号：EP85104945.2
申请日：1985-04-23
CPC分类号： G11C29/76 , G06F2201/81 , G11C16/04 , G11C29/02 , G11C29/025 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/82
摘要： Das System enthält einen Mikrocomputer (µC), der in bestimmten Abständen unter Verwendung einer in einem EEPROM integrierten Klassifizierungsschaltung die Speicherzellen des EEPROMs auf Änderungen der Schwellwerte durchmißt und im Falle des Feststellens eines Fehlers in einer somit als fehlerhaft erkannten Zeile oder Spalte diese fehlerhafte Zeile bzw. Spalte, deren Adresse dann in einem Bereich (B2) gespeichert wird, durch eine redundante Zeil bzw. Spalte in einem anderen Bereich (B1) unter Verwendung eines Korrekturregisters (K) ersetzt.
摘要翻译： 该系统包括通过使用内置的EEPROM分类电路，EEPROM的存储器单元的阈值值的变化和或以在一个由此识别为这个缺陷线的有缺陷的行或列中检测到错误的情况下以预定的间隔测量得到的微型电子计算机（.mu.C） 列中，在一个区域（B2）为地址使用置换后的校正寄存器（K）被存储时，通过一冗余列采尔或在另一区域（B1）。
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公开(公告)号：EP0172593A3
公开(公告)日：1986-03-05
申请号：EP85201238
申请日：1985-07-26
发明人： Bosnyak, Bob , Chan, Albert , Fitzpatrick, Mark , Gouldsberry, Gary , Tsui, Cyrus , Chan, Andrew K.
CPC分类号： G11C29/50008 , G01R31/025 , G11C17/14 , G11C29/02 , G11C29/50
摘要： Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.
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公开(公告)号：EP0146975A2
公开(公告)日：1985-07-03
申请号：EP84200830.2
申请日：1984-06-09
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C17/14 , G11C29/02 , G11C29/50 , G11C2029/5006
摘要： Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.
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