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    Memory module with reduced access granularity
    76.
    发明公开
    Memory module with reduced access granularity 审中-公开
    Speichermodul mit verminderterZugriffsgranularität

    公开(公告)号：EP2413327A1

    公开(公告)日：2012-02-01

    申请号：EP11184623.4

    申请日：2007-04-30

    申请人： Rambus Inc.

    发明人： Hampel, Craig E. ,  Ware, Frederick A.

    IPC分类号： G11C7/10 ,  G06F13/16 ,  G11C5/04 ,  G06F13/42

    CPC分类号： G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

    摘要： A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

    摘要翻译： 具有减小的访问粒度的存储器模块。 存储器模块包括其上具有信号线的衬底，其形成控制路径和第一和第二数据路径，并且还包括共同耦合到控制路径并分别耦合到第一和第二数据路径的第一和第二存储器件。 第一和第二存储器件包括控制电路，用于经由控制路径接收相应的第一和第二存储器访问命令，并且响应于第一和第二存储器访问命令在第一和第二数据路径上实现并发数据传输。

    MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS
    77.
    发明授权
    MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS 有权
    多端口，不同的端口速度存储设备

    公开(公告)号：EP2008281B1

    公开(公告)日：2012-01-25

    申请号：EP07759902.5

    申请日：2007-03-30

    申请人： Silicon Image, Inc.

    发明人： LEE, Dongyun ,  CHO, Myung, Rai ,  KIM, Sungjoon

    IPC分类号： G11C7/10 ,  G11C8/16

    CPC分类号： G11C8/16 ,  G06F13/4054 ,  G06F13/4243 ,  G11C7/1075 ,  G11C2207/108

    摘要： A multi-port memory device (100) having two or more ports (110) wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock (SCK) and a port clock (PCK). The system clock is applied to port logic (220) that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit (230) that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.

    PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE
    79.
    发明公开
    PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE 有权
    渐进式LEISTUNGSSTEUERUNG EINER SPEICHERVORRICHTUNG MIT MEHRERENANSCHLÜSSEN

    公开(公告)号：EP2135249A4

    公开(公告)日：2010-08-18

    申请号：EP08744214

    申请日：2008-03-21

    申请人： SILICON IMAGE INC

    发明人： KIM SUNGJOON ,  LEE DONGYUN ,  KIM EDWARD

    IPC分类号： G11C5/14 ,  G11C7/10

    CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1075 ,  G11C7/22 ,  Y02D10/14 ,  Y02D50/20

    摘要： A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.

    摘要翻译： 提供了一种逐渐降低串行存储设备功耗的方法和系统，称为功率控制系统。 电源控制系统监视多端口串行存储器的端口，以便可以在每个端口的基础上启用或禁用它们。 当在端口上没有发送或接收数据时，采取一系列步骤逐步对端口的部分断电，并使端口进入低功率状态。 通过禁用某些端口并将端口置于低功耗状态，整个串行端口存储器的功耗显着降低。