公开(公告)号：EP3080843A1

公开(公告)日：2016-10-19

申请号：EP14850960.7

申请日：2014-09-26

申请人： Texas Instruments Incorporated

发明人： DENISON, Marie ,  PENDHARKAR, Sameer ,  MATHUR, Guru

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

摘要： A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

摘要翻译： 具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构以形成晶体管的垂直漂移区域而形成，使得每个垂直漂移区域通过深沟槽结构在至少两个相对侧上界定。 深沟槽结构间隔开以形成漂移区域的RESURF区域。 在垂直漂移区域上的衬底中的沟槽中形成沟槽栅极。 身体区域位于垂直漂移区域上的衬底中。

公开(公告)号：EP2897174A4

公开(公告)日：2016-05-18

申请号：EP13836438

申请日：2013-07-04

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HAYASHI HIDEKI ,  MASUDA TAKEYOSHI

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L29/66666 ,  H01L21/02529 ,  H01L21/02636 ,  H01L21/049 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

公开(公告)号：EP2901485A1

公开(公告)日：2015-08-05

申请号：EP13840258.1

申请日：2013-06-12

申请人： Intel Corporation

发明人： DEWEY, Gilbert ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  MUKHERJEE, Niloy

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body (206) with a channel region. A source and drain material region (226) is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack (220, 222, 224) is disposed in the trench and on the exposed portion of the channel region. The gate stack includes a first dielectric layer (220) on outer portions of the channel region (206), a second dielectric layer (222) on an inner portion of the channel region, and a gate electrode (224).

公开(公告)号：EP2846348A1

公开(公告)日：2015-03-11

申请号：EP14181035.8

申请日：2014-08-14

申请人： Renesas Electronics Corporation

发明人： Mizutani, Masaharu ,  Inoue, Masao ,  UMEDA, Hiroshi ,  Kadoshima, Masaru

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/792 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02318 ,  H01L21/02359 ,  H01L21/28229 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66833

摘要： The performance of a semiconductor device having a memory element is improved. An insulating film (MZ), which is a gate insulating film for a memory element, is formed on a semiconductor substrate (SB), and a gate electrode (MG) for the memory element is formed on the insulating film. The insulating flm has a first insulating film (AOX1), a second insulating film (HSO) thereon, and a third insulating film (AOX2) thereon. The second insulating film (HSO) is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film (AOX 1, 2) has a band gap larger than the band gap of the second insulating film and is formed, for example, from aluminum oxide. An additional interface layer (OX1) may be present between substrate and insulating film.

摘要翻译： 提高了具有存储元件的半导体器件的性能。 作为存储元件的栅极绝缘膜的绝缘膜（MZ）形成在半导体基板（SB）上，在绝缘膜上形成有用于存储元件的栅电极（MG）。 绝缘膜具有第一绝缘膜（AOX1），第二绝缘膜（HSO）及其上的第三绝缘膜（AOX2）。 第二绝缘膜（HSO）是具有电荷积聚功能并含有铪，硅和氧的高介电常数绝缘膜。 第一绝缘膜和第三绝缘膜（AOX1,2）中的每一个具有比第二绝缘膜的带隙大的带隙，并且例如由氧化铝形成。 在衬底和绝缘膜之间可以存在另外的界面层（OX1）。

公开(公告)号：EP2639818A2

公开(公告)日：2013-09-18

申请号：EP13157686.0

申请日：2013-03-04

申请人： Renesas Electronics Corporation

发明人： Kaneoka, Tatsunori ,  Kawahara, Takaaki

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode (MG) is formed over a semiconductor substrate (1) via an insulating film (5). The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film (5a), a silicon nitride film (5b) over the first silicon oxide film, and a second silicon oxide film (5c) over the silicon nitride film. Metal elements (6) exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1 × 10 13 to 2 × 10 14 atoms/cm 2 .

摘要翻译： 提供具有改进的电性能的具有非易失性存储器的半导体器件。 存储器栅极电极（MG）经由绝缘膜（5）形成在半导体衬底（1）上。 绝缘膜是其中具有电荷存储部分的绝缘膜，并且包括第一氧化硅膜（5a），在第一氧化硅膜上的氮化硅膜（5b）以及在第一氧化硅膜上的第二氧化硅膜（5c） 氮化硅膜。 金属元素（6）存在于氮化硅膜与第二氧化硅膜之间或氮化硅膜中，表面密度为1×1013至2×1014原子/ cm2。

公开(公告)号：EP2633556A2

公开(公告)日：2013-09-04

申请号：EP11834971.1

申请日：2011-10-18

申请人： Micron Technology, Inc.

发明人： BREWER, Rhett T. ,  RAMASWAMY, Durai V.

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  G11C14/0018 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/244 ,  H01L21/265 ,  H01L21/28273 ,  H01L21/44 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881

摘要： Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.

摘要翻译： 包括其中具有吸气剂的电荷存储结构的存储器单元可用于非易失性存储器装置。 提供从电荷存储结构的电荷存储材料吸收氧气可以有助于缓解电荷存储材料的有害氧化。

公开(公告)号：EP2240956A1

公开(公告)日：2010-10-20

申请号：EP08869950.9

申请日：2008-12-31

申请人： ST Microelectronics (Rousset) SAS

发明人： FORNARA, Pascal

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  G04F10/10 ,  G11C16/04 ,  H01L29/423 ,  H01L29/51

CPC分类号： G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

摘要： The invention relates to an EEPROM memory cell that comprises a dual-gate MOS transistor in which the two gates (87, 98) are separated by an insulation layer, characterised in that the insulation layer includes a first portion (89) and a second portion (96) having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.

公开(公告)号：EP1451877A4

公开(公告)日：2009-06-03

申请号：EP02786713

申请日：2002-11-13

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/513 ,  H01L29/7813

摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

公开(公告)号：EP1856724A4

公开(公告)日：2009-03-11

申请号：EP06720394

申请日：2006-02-08

申请人： FREESCALE SEMICONDUCTOR INC

发明人： LIM SANGWOO ,  GRUDOWSKI PAUL A ,  LUO TIEN YING ,  ADETUTU OLUBUNMI O ,  TSENG HSING H

IPC分类号： H01L21/3205 ,  H01L21/31 ,  H01L21/336

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

公开(公告)号：EP1728279A2

公开(公告)日：2006-12-06

申请号：EP05708868.4

申请日：2005-02-28

申请人： Koninklijke Philips Electronics N.V.

发明人： KOOPS, G.E., Philips Intel. Prop. & Standards ,  IN'T ZANDT, M.A.A., Philips Intel. Prop.& Standars

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7811

摘要： A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.