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81.发明授权
公开(公告)号：EP1380113B1
公开(公告)日：2007-05-09
申请号：EP01969719.2
申请日：2001-09-14
CPC分类号： H03M1/0678 , H03M1/742
摘要： Electronic circuitry comprising a data processing circuit for processing a digital signal (DS), such as a digital to analog converter (DAC), and a current compensation circuit (CMP). Both the digital to analog converter (DAC) and the current compensation circuit (CMP) are powered by a single power supply (U1). The current taken from the power supply (U1) by the digital to analog converter (DAC) is normally dependent on the digital input signal (DS). This would lead to distortion since the loss-resistances (Rl1, Rl2) which are always present in series with the power supply (U1) then feed a data-dependent supply voltage (U2) to the digital to analog converter (DAC). This problem is overcome by the addition of the current compensation circuit (CMP) which is coupled for receiving the digital signal (DS). The current compensation circuit (CMP) is arranged in such a way that the sum of the data-dependent current drawn by the digital to analog converter (DAC) and the data-dependent current drawn by the compensation circuit (CMP) is substantially independent of the data.
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公开(公告)号：EP1222741B1
公开(公告)日：2005-08-31
申请号：EP00964860.1
申请日：2000-09-15
发明人： WIKNER, Jacob , VESTERBACKA, Mark
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/0663 , H03M1/0673 , H03M1/745
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公开(公告)号：EP1386402A1
公开(公告)日：2004-02-04
申请号：EP02769266.4
申请日：2002-04-12
申请人： Analog Devices, Inc.
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , H03M1/36
摘要： An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.
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84.发明公开
公开(公告)号：EP1380113A2
公开(公告)日：2004-01-14
申请号：EP01969719.2
申请日：2001-09-14
IPC分类号： H03M1/06
CPC分类号： H03M1/0678 , H03M1/742
摘要： Electronic circuitry comprising a data processing circuit for processing a digital signal (DS), such as a digital to analog converter (DAC), and a current compensation circuit (CMP). Both the digital to analog converter (DAC) and the current compensation circuit (CMP) are powered by a single power supply (U1). The current taken from the power supply (U1) by the digital to analog converter (DAC) is normally dependent on the digital input signal (DS). This would lead to distortion since the loss-resistances (Rl1, Rl2) which are always present in series with the power supply (U1) then feed a data-dependent supply voltage (U2) to the digital to analog converter (DAC). This problem is overcome by the addition of the current compensation circuit (CMP) which is coupled for receiving the digital signal (DS). The current compensation circuit (CMP) is arranged in such a way that the sum of the data-dependent current drawn by the digital to analog converter (DAC) and the data-dependent current drawn by the compensation circuit (CMP) is substantially independent of the data.
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公开(公告)号：EP0874326A3
公开(公告)日：1999-09-22
申请号：EP98302851.5
申请日：1998-04-14
发明人： Liu, Edward W.
CPC分类号： H03M1/0678 , G06J1/00 , H03M3/35 , H03M3/458 , H03M3/50
摘要： A method of canceling noise in analog circuits is described along with noise cancellation circuits. Analog circuits are sensitive to noise. Especially in mixed signal environments where digital circuits and analog circuits are combined, the noise generated by relatively noisy digital circuits often cause the analog circuits to produce incorrect output signals. Instead of shielding or separating the susceptible analog circuits from noisy digital circuits, additional circuitry is added where one of the added circuits, denoted as the noise separator circuit, produce only the noise component of the output signal, the first output, of the analog circuit adversely affected by the noise. Then, another circuit is used to subtract the noise from the first output, thereby producing a noise-free output signal. Alternatively, the noise separator circuit can be made to produce the inverse of the first output, including the inverse of the noise. Then, the first output and the inverse output can be added and halved to produce the desired, noise-free output.
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公开(公告)号：EP0932936A1
公开(公告)日：1999-08-04
申请号：EP98935670.0
申请日：1998-07-16
发明人： COOPER, Russell, E.
IPC分类号： H03M1
CPC分类号： H03M1/0678 , H03M1/08 , H03M1/46
摘要： Apparatus and method are disclosed for successive approximation analog-to-digital conversion of a variable analog input voltage to digital form by periodic sampling thereof, using a comparator to compare the relative values of the analog input voltage amplitude in a predetermined time interval and the upper limit of a reference voltage range which is successively adjusted until it closely approximates the digital value of the sampled analog input voltage in that time interval. The successive adjustment is performed by a successive approximation register which has an odd number of multiple stages, at least three, for each digital significant bit representing the upper limit of the reference voltage range to be used in the comparison. The accuracy and reliability of this upper limit is refined by using as the value of each significant bit the majority of its value in the multiple stages. After a number of comparisons that fixes the majority value of each significant bit, the resulting succession of the significant bits becomes the digital conversion of the analog input voltage in the respective time interval.
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公开(公告)号：EP0562564A3
公开(公告)日：1997-04-02
申请号：EP93104794.8
申请日：1993-03-23
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , H03M1/365
摘要： Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array, whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.
摘要翻译： 链路电容器用于在反相器斩波比较器阵列中建立耦合电容器和反相器的接合点之间的连接，以便减少由于馈通引起的注入的电荷变化。 布置在比较器阵列的每一端的比较器阵列中的一些比较器构成冗余比较器阵列，而不连接到用于获得A / D转换输出的逻辑电路。 这降低了比较器阵列中的器件参数变化的影响，从而实现了高精度电压比较，并提高了抗噪声强度。
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公开(公告)号：EP0423988B1
公开(公告)日：1997-03-12
申请号：EP90310918.9
申请日：1990-10-04
发明人： Epstein, Howard C.
CPC分类号： H03M1/0678 , G01D5/366 , H03M1/308
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89.发明公开
公开(公告)号：EP0738439A1
公开(公告)日：1996-10-23
申请号：EP95905844.0
申请日：1994-12-30
IPC分类号： H03M1
CPC分类号： H03M1/0678 , H03M1/822
摘要： A digital-to-analog (D/A) converter eliminates matching requirements and does not generate harmonics or noise. The D/A converter has an array of injectors for converting an input word to an analog voltage. A plurality of clocked switches discharge the injector array and the feedback path when switched into a first phase position and transfer the injector signal across the feedback path to the output of the D/A converter when switched to a second phase position. The conversion period, the time in which the digital input word is converted to an analog output voltage, is divided into N-1 subperiods. Each injector is enabled once or not at all for each subperiod such that the weighted signal injected during a single conversion period is constant and such that all the injectors in the array contribute an equal amount of signal during a conversion period.
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公开(公告)号：EP0610627A2
公开(公告)日：1994-08-17
申请号：EP93309908.7
申请日：1993-12-09
发明人： Kuwano, Hiromichi, Japan Texas Instruments Co. Ltd , Tahara, Hisashi, Japan Texas Instruments Co. Ltd
IPC分类号： H03M1/36
CPC分类号： H03M1/148 , H03M1/0678 , H03M1/0682 , H03M1/365
摘要： Purpose
To guarantee a high conversion speed and resolution while greatly reducing the number of circuit elements.
Constitution
The A/D converter shown in Figure 1 is a 6-bit resolution flash A/D converter made up of a 3-bit lower A/D conversion section and a 3-bit upper A/D conversion section. This lower A/D conversion section has a stage 1 comparator section 10, containing a specified number of comparators which compare the analog signal to comparison reference voltages of differing values, stepped in equal increments, an adder 12 which combines, in a specified relationship, the outputs from each of the comparators in this stage 1 comparator section 10 and adds them in each group, a second comparator section 14 which combines, in a specified relationship, the specified number of addition results from this adder 12 into pairs and compares these pairs, and a pre-encoder 16, which converts the specified number of comparison results obtained by second comparator section 14 into 8 binary logical outputs which can be interpreted by lower encoder 18.摘要翻译： 目的确保高转换速度和分辨率，同时大大减少电路元件的数量。 结构图1所示的A / D转换器是由3位下A / D转换部分和3位上A / D转换部分组成的6位分辨率闪存A / D转换器。 该较低A / D转换部分具有级1比较器部分10，其包含指定数量的比较器，其将模拟信号与以相等增量步进的不同值的比较参考电压进行比较，加法器12以指定的关系组合， 来自该级1比较器部分10中的每个比较器的输出并将它们相加在每个组中，第二比较器部分14以指定的关系将来自该加法器12的指定数目的相加结果组合成对并将其对 ，以及预编码器16，其将由第二比较器部分14获得的指定数量的比较结果转换成可由下编码器18解释的8个二进制逻辑输出。
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