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2671 条记录 (耗时 0.034 秒)

    MULTI-CHIP PACKAGING
    81.
    发明公开
    MULTI-CHIP PACKAGING 审中-公开

    公开(公告)号：EP3982407A3

    公开(公告)日：2022-07-20

    申请号：EP21210501.9

    申请日：2019-05-03

    申请人： INTEL Corporation

    发明人： SANKMAN, Robert ,  AGRAHARAM, Sairam ,  OU, Shengquan ,  DE BONIS, Thomas ,  SPENCER, Todd ,  SUN, Yang ,  WANG, Guotao

    IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L21/60

    摘要： An electronic device including a first die (110) that includes a first set of die contacts (230). The electronic device includes a second die (120) that includes a second set of die contacts (260). The electronic device includes a bridge interconnect (140) that includes a first set of bridge contacts (310) and a second set of bridge contacts (320). The first set of bridge contacts are directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts are directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect helps facilitate electrical communication between the first die and the second die.

    CHIP PACKAGE STRUCTURE, PREPARATION METHOD, AND ELECTRONIC DEVICE
    82.
    发明公开
    CHIP PACKAGE STRUCTURE, PREPARATION METHOD, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP4027384A2

    公开(公告)日：2022-07-13

    申请号：EP22150307.1

    申请日：2022-01-05

    申请人： HUAWEI TECHNOLOGIES CO., LTD.

    发明人： DENG, Chaojun ,  WEI, Xiaoyun ,  YANG, Yong

    IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L23/485 ,  H01L21/60

    摘要： This application discloses a chip package structure, a preparation method, and an electronic device, and pertains to the field of chip package technologies. The chip package structure includes a glass substrate, a routing layer, and at least one die; a first surface of the glass substrate has solder joints, a second surface of the glass substrate has substrate solder balls, the routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer; and each die has chip solder balls, the at least one die is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. This application can improve connection reliability between the die and the glass substrate, and can reduce a signal transmission loss.

    STACKED CHIP PACKAGE AND TERMINAL DEVICE
    83.
    发明公开
    STACKED CHIP PACKAGE AND TERMINAL DEVICE 审中-公开

    公开(公告)号：EP4024450A1

    公开(公告)日：2022-07-06

    申请号：EP19947913.0

    申请日：2019-09-30

    申请人： Huawei Technologies Co., Ltd.

    发明人： ZHANG, Xiaodong ,  ZHANG, Tonglong ,  LI, Heng ,  WANG, Simin

    IPC分类号： H01L25/065 ,  H01L23/528

    摘要： This application provides a chip stacking package and a terminal device, and relates to the field of semiconductor technologies. The chip stacking package can resolve a problem of high costs caused by using a through silicon via technology while ensuring a power supply requirement. The chip stacking package (01) includes a first chip (101) and a second chip (102) disposed between a first routing structure (10) and a second routing structure (20). An active surface (S1) of the first chip (101) faces an active surface (S2) of the second chip (102). The active surface (S1) of the first chip (101) includes a first overlapping region (A1) and a first non-overlapping region (C1). The active surface (S2) of the second chip (102) includes a second overlapping region (A2) and a second non-overlapping (C2) region. The first overlapping region (A1) overlaps the second overlapping region (A2), and the first overlapping region (A1) is connected to the second overlapping region (A2). The first non-overlapping region (C1) is connected to the second routing structure (20). The second non-overlapping region (C2) is connected to the first routing structure (10).

    PACKAGE SYSTEM AND PACKAGE
    84.
    发明公开
    PACKAGE SYSTEM AND PACKAGE 审中-公开

    公开(公告)号：EP4020711A1

    公开(公告)日：2022-06-29

    申请号：EP21195238.7

    申请日：2021-09-07

    申请人： INTEL Corporation

    发明人： ACIKALIN, Tolga ,  FOUST, Kenneth ,  CHIU, Chia-Pin ,  YANG, Tae-Young ,  ZHOU, Zhen ,  LIU, Renzhi ,  ESCOBAR PELAEZ, Johanny ,  CHIN, Cheng-Yuan

    IPC分类号： H01Q15/00 ,  H01Q15/14 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/03

    摘要： In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.

    HYBRID DEVICE ASSEMBLIES AND METHOD OF FABRICATION
    89.
    发明公开
    HYBRID DEVICE ASSEMBLIES AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：EP3998625A2

    公开(公告)日：2022-05-18

    申请号：EP21201118.3

    申请日：2021-10-06

    申请人： NXP USA, Inc.

    发明人： Li, LI ,  Viswanathan, Lakshminarayan ,  Jones, Jeffrey Kevin

    IPC分类号： H01L21/60 ,  H01L23/13 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L29/06 ,  H01L23/552

    摘要： A device assembly includes a functional substrate (32) having one or more electronic components (34) formed there. The functional substrate has a cavity (40) extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die (42) placed within the cavity with a pad surface (44) of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.