公开(公告)号：EP2370996B1

公开(公告)日：2020-05-13

申请号：EP09836647.9

申请日：2009-12-02

申请人： ASM America, Inc.

发明人： DARABNIA, Buz ,  YEDNAK, Andy ,  HALPIN, Mike ,  JACOBS, Loren ,  AGGARWAL, Ravinder

IPC分类号： C23C16/46 ,  G01K13/00 ,  G01K7/04

公开(公告)号：EP1887617A3

公开(公告)日：2015-07-29

申请号：EP07022300.3

申请日：2002-02-12

申请人： ASM America, Inc.

发明人： Todd, Michael A.

IPC分类号： H01L21/205 ,  C23C16/00

摘要： Trisilane is used in chemical vapor deposition methods to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

公开(公告)号：EP2353176A2

公开(公告)日：2011-08-10

申请号：EP09825280.2

申请日：2009-11-02

申请人： ASM America, Inc.

发明人： GIVENS, Michael ,  GOODMAN, Matthew, G. ,  HAWKINS, Mark ,  HALLECK, Brad ,  TERHORST, Herbert

IPC分类号： H01L21/205 ,  H01L21/00

CPC分类号： H01L21/6719 ,  C23C16/45504 ,  C23C16/45589 ,  C23C16/45591

摘要： A reaction chamber having a reaction spaced defined therein, wherein the reaction space is tunable to produce substantially stable and laminar flow of gases through the reaction space. The substantially stable and laminar flow is configured to improve the uniformity of deposition on substrates being processed within the reaction chamber to provide a predictable deposition profile.

公开(公告)号：EP1956112A3

公开(公告)日：2008-10-22

申请号：EP08006163.3

申请日：1999-06-30

申请人： ASM America, Inc.

发明人： Doley, Allan D. ,  Goodwin, Dennis L. ,  O'Neill, Kenneth ,  Vrijburg, Gerben ,  Rodriguez, David ,  Aggarwal, Ravinder

IPC分类号： C23C16/00 ,  C30B23/06 ,  C23C16/44 ,  C23C16/54

CPC分类号： C30B29/14 ,  C23C16/4401 ,  C23C16/4408 ,  C30B25/08 ,  Y10S414/139

摘要： An apparatus and method for reducing particles in reactors. The apparatus (10) includes an enclosure for processing the semiconductor wafers. The enclosure has a wafer handling chamber (16) connected by an isolation gate valve (18) to a load lock chamber (14). Additionally, the apparatus includes: a reactor chamber (38) pipes (24,26) for delivering a purge gas into the wafer handling chamber (16); a pilot operated back pressure regulator (40) for regulating the delivery and removal of the purge gas from the enclosure for reducing disturbances from the purge gas entering into the enclosure; a flow regulated Bernoulli wand (36) for lifting and holding a single wafer; ionizers (21a-21d) in the purge gas lines entering the wafer handling chamber (16) and load locks chamber (14) for ionizing the purged gas molecules, the ionized gas discharges all the static inside the semiconductor equipment and prevents the wafer from attracting charged particles; and means for reducing gas flow turbulence when switching valves within the reactor.

公开(公告)号：EP1956113A1

公开(公告)日：2008-08-13

申请号：EP08000724.8

申请日：2008-01-16

申请人： ASM America, Inc.

发明人： Elers, Kai-Erik

IPC分类号： C23C16/455 ,  C23C16/30

CPC分类号： C23C16/34 ,  C23C16/4554

摘要： Methods of controllably producing conductive tantalum nitride films are provided. The methods comprise contacting a substrate in a reaction space with alternating and sequential pulses of a tantalum source material, plasma-excited species of hydrogen and nitrogen source material. The plasma-excited species of hydrogen reduce the oxidation state of tantalum, thereby forming a substantially conductive tantalum nitride film over the substrate. In some embodiments, the plasma-excited species of hydrogen react with and removes halide residues in a deposited metallic film.

摘要翻译： 提供可控制造导电氮化钽膜的方法。 所述方法包括使反应空间中的衬底与钽源材料，等离子体激发的氢和氮源材料的交替和顺序脉冲接触。 氢等离子体激发的物质降低钽的氧化态，从而在衬底上形成基本导电的氮化钽膜。 在一些实施方案中，氢等离子体激发的物质与沉积的金属膜中的卤化物残留物反应并除去其中的残留物。

公开(公告)号：EP1956112A2

公开(公告)日：2008-08-13

申请号：EP08006163.3

申请日：1999-06-30

申请人： ASM America, Inc.

发明人： Doley, Allan D. ,  Goodwin, Dennis L. ,  O'Neill, Kenneth ,  Vrijburg, Gerben ,  Rodriguez, David ,  Aggarwal, Ravinder

IPC分类号： C23C16/00 ,  C30B23/06 ,  C23C16/44 ,  C23C16/54

CPC分类号： C30B29/14 ,  C23C16/4401 ,  C23C16/4408 ,  C30B25/08 ,  Y10S414/139

摘要： An apparatus and method for reducing particles in reactors. The apparatus (10) includes an enclosure for processing the semiconductor wafers. The enclosure has a wafer handling chamber (16) connected by an isolation gate valve (18) to a load lock chamber (14). Additionally, the apparatus includes: a reactor chamber (38) pipes (24,26) for delivering a purge gas into the wafer handling chamber (16); a pilot operated back pressure regulator (40) for regulating the delivery and removal of the purge gas from the enclosure for reducing disturbances from the purge gas entering into the enclosure; a flow regulated Bernoulli wand (36) for lifting and holding a single wafer; ionizers (21a-21d) in the purge gas lines entering the wafer handling chamber (16) and load locks chamber (14) for ionizing the purged gas molecules, the ionized gas discharges all the static inside the semiconductor equipment and prevents the wafer from attracting charged particles; and means for reducing gas flow turbulence when switching valves within the reactor.

摘要翻译： 一种减少反应器中颗粒的装置和方法。 该设备（10）包括用于处理半导体晶片的外壳。 外壳具有通过隔离闸阀（18）连接到加载锁定室（14）的晶片处理室（16）。 另外，该设备包括：用于将清除气体输送到晶片处理室（16）中的反应室（38）管道（24,26）; 先导式背压调节器（40），其用于调节来自外壳的清除气体的输送和去除，以减少来自进入外壳的清除气体的干扰; 用于提升和保持单个晶片的流量调节伯努利棒（36）; 进入晶片处理室（16）的净化气体管线中的离子发生器（21a-21d）和用于离子化净化气体分子的负载锁定室（14），离子化气体释放半导体设备内部的全部静电并防止晶片吸引 带电粒子; 以及用于在切换反应器内的阀时减少气流湍流的装置。

公开(公告)号：EP1851794A1

公开(公告)日：2007-11-07

申请号：EP06735499.3

申请日：2006-02-21

申请人： ASM America, Inc.

发明人： SPREY, Hessel ,  FUKUDA, Hideaki, Tsuduki-ku ,  KEMELING, Nathanael R.C. ,  GOUNDAR, Kamal Kishore ,  KUMAR, Davendra ,  STOKHOF, Maarten

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/02063 ,  C23C14/02 ,  C23C16/02 ,  C23C16/36 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873

摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed (100) in insulating layers. The layers are then adequately treated with a particular plasma process (101). Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction (115) can occur without significantly filling the pores forming improved interconnects.

公开(公告)号：EP1846595A1

公开(公告)日：2007-10-24

申请号：EP06719933.1

申请日：2006-01-31

申请人： ASM America, Inc.

发明人： BAUER, Matthias ,  ARENA, Chantal ,  BERTRAM, Ronald ,  TOMASINI, Pierre ,  CODY, Nyles ,  BRABANT, Paul ,  ITALIANO, Joseph ,  JACOBSON, Paul ,  WEEKS, Keith, Doran

IPC分类号： C30B29/06 ,  C30B25/02 ,  C23C16/24 ,  H01L29/10 ,  H01L21/205 ,  C23C16/448

CPC分类号： H01L29/7848 ,  C23C16/04 ,  C23C16/22 ,  C23C16/24 ,  C23C16/32 ,  C23C16/325 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/32056 ,  H01L21/3215 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.

公开(公告)号：EP1837899A2

公开(公告)日：2007-09-26

申请号：EP07005880.5

申请日：2007-03-22

申请人： ASM America, Inc.

发明人： Brabant, Paul D. ,  Weeks, Keith Doran

IPC分类号： H01L21/20

CPC分类号： C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262

摘要： Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.

摘要翻译： 本发明的一些实施方案涉及制造半导体。 公开了提供薄且完全松弛的SiGe层的方法和装置。 在一些实施方案中，在单晶结构和SiGe异质外延层之间和/或SiGe异质外延层内的存在使SiGe层变薄并完全松弛。 在一些实施例中，Si的应变层可以沉积在完全松弛的SiGe层上。

公开(公告)号：EP1738001A2

公开(公告)日：2007-01-03

申请号：EP05780034.4

申请日：2005-04-21

申请人： ASM America, Inc.

发明人： BAUER, Matthias

IPC分类号： C30B1/00 ,  H01L21/469 ,  H01L21/31 ,  H01L21/36 ,  H01L21/20

CPC分类号： C30B25/02 ,  C30B25/16 ,  C30B29/52 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28525 ,  H01L21/28562

摘要： A method for depositing an in situ doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 80 torr in a process chamber housing a patterned substrate. The method further comprises providing a flow of dichlorosilane to the process chamber. The method further comprises providing a flow of a dopant hydride to the process chamber. The method further comprises selectively depositing the epitaxial semiconductor layer on single crystal material on the patterned substrate at a rate of greater than about 3 nm min-1.