公开(公告)号：EP0778623B1

公开(公告)日：2001-07-18

申请号：EP96307350.7

申请日：1996-10-09

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L21/82

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/7885

公开(公告)号：EP0965133A1

公开(公告)日：1999-12-22

申请号：EP98950996.0

申请日：1998-10-07

申请人： Programmable Microelectronics Corporation

发明人： CHANG, Shang-De, Ted ,  KOWSHIK, Vikram ,  YU, Andy, Teng-Feng ,  RADJY, Nader

IPC分类号： G11C16 ,  H01L21 ,  H01L27 ,  H01L29

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L29/7885

摘要： A nonvolatile memory array has a plurality of PMOS two transistor (2T) memory cells. Each 2T cell (40) includes a PMOS floating gate transistor (40a) and a PMOS select transistor (40b) and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n-well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

公开(公告)号：EP0774788B1

公开(公告)日：2001-08-01

申请号：EP96307875.3

申请日：1996-10-30

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/7881 ,  H01L29/7887

公开(公告)号：EP0854509A1

公开(公告)日：1998-07-22

申请号：EP98100462.5

申请日：1998-01-13

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De Ted, Progr. Microelectronics Corp. ,  Ly, Binh, Programmable Microelectronics Corp.

IPC分类号： H01L21/8239

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

摘要翻译： 一种半导体制造工艺允许高电压晶体管，逻辑晶体管和存储单元的制造，其中，根据需要用于子0.3微米设备的几何形状，所述逻辑晶体管的栅极氧化比非的隧道氧化物厚度薄 易失性存储器细胞，而不在存储器单元的隧道氧化物的逻辑晶体管或污染的栅极氧化物的不希望的污染。 在一个，实施例的存储器单元的隧道氧化物生长到厚度希望的。 在下一步骤中的，而这些用作存储单元（多个）的浮栅掺杂的多晶硅层被立即沉积在存储器单元的隧道氧化物，由此保护隧道氧化物从污染在随后的掩模和蚀刻步骤。 则逻辑晶体管和高电压晶体管的栅氧化物的栅氧化层生长到厚度希望的。

公开(公告)号：EP0778623A2

公开(公告)日：1997-06-11

申请号：EP96307350.7

申请日：1996-10-09

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L21/82

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/7885

摘要： A P-channel MOS memory cell has P+ source (14) and drain (16) regions formed in an N-well (18). A thin tunnel oxide (24) is provided between the well surface and an overlying floating gate (22). In one embodiment, the thin tunnel oxide (24) extends over a substantial portion of the active region (12) of the device. An overlying control gate (26) is insulated from the floating gate (22) by an insulating layer (28). The device is programmed via hot electron injection from the drain end of the channel region (12) to the floating gate (22), without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate (22) to the N-well (18) with the source (14), drain (16), and N-well (18) regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

摘要翻译： P沟道MOS存储单元具有形成在N阱（18）中的P +源极（14）和漏极（16）区域。 在阱表面和上面的浮置栅极（22）之间提供薄隧道氧化物（24）。 在一个实施例中，薄隧道氧化物（24）在器件的有源区（12）的大部分上延伸。 覆盖的控制栅极（26）通过绝缘层（28）与浮置栅极（22）绝缘。 器件通过从沟道区域（12）的漏极端到浮置栅极（22）的热电子注入而被编程，而不会发生雪崩击穿，这允许单元在编程期间是位选择的。 擦除是通过从源极（14），漏极（16）和N阱（18）区域等偏置的，从浮栅（22）到N阱（18）的电子隧道实现的。 由于不存在高的漏极/阱结偏置电压，因此可以降低单元的沟道长度而不会产生破坏性的结应力。

公开(公告)号：EP0965133A4

公开(公告)日：2003-02-05

申请号：EP98950996

申请日：1998-10-07

申请人： PROGRAMMABLE MICROELECTRONICS

发明人： CHANG SHANG-DE TED ,  KOWSHIK VIKRAM ,  YU ANDY TENG-FENG ,  RADJY NADER

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L29/7885

摘要： A nonvolatile memory array has a plurality of PMOS two transistor (2T) memory cells. Each 2T cell (40) includes a PMOS floating gate transistor (40a) and a PMOS select transistor (40b) and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n-well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

公开(公告)号：EP0776049B1

公开(公告)日：2000-08-30

申请号：EP96308360.5

申请日：1996-11-19

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

公开(公告)号：EP0778623A3

公开(公告)日：1997-09-03

申请号：EP96307350.7

申请日：1996-10-09

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L21/82

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/7885

摘要： A P-channel MOS memory cell has P+ source (14) and drain (16) regions formed in an N-well (18). A thin tunnel oxide (24) is provided between the well surface and an overlying floating gate (22). In one embodiment, the thin tunnel oxide (24) extends over a substantial portion of the active region (12) of the device. An overlying control gate (26) is insulated from the floating gate (22) by an insulating layer (28). The device is programmed via hot electron injection from the drain end of the channel region (12) to the floating gate (22), without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate (22) to the N-well (18) with the source (14), drain (16), and N-well (18) regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

公开(公告)号：EP0776049A1

公开(公告)日：1997-05-28

申请号：EP96308360.5

申请日：1996-11-19

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： A P-channel single-poly non-volatile memory cell (10) having P+ source (20) and P+ drain regions (22) and a channel (30) extending therebetween is formed in an N-type well (12). An overlying poly-silicon floating gate (26) is separated from the N-well by a thin oxide layer (34). A P-type diffusion region (36) is formed in a portion of the N-well underlying the floating gate (26) and is thereby capacitively coupled to the floating gate (26). This P-type diffusion area serves as the control gate for the cell.
Programming is accomplished by coupling a sufficient voltage to the floating gate (26) via the control gate (36) while biasing the source (20) and drain (22) regions so as to cause the tunneling of electrons from the P+ drain region (22) of the cell to the floating gate (26). In some embodiments, an additional P-type diffusion region underlying the floating gate and separated therefrom by a layer of tunnel oxide serve as an erase gate for the memory cell. In such embodiments, erasing of the cell is accomplished by causing electrons to tunnel from the floating gate to the erase gate.

摘要翻译： 在N型阱（12）中形成有具有P +源极（20）和P +漏极区域（22）以及在其间延伸的沟道（30）的P沟道单晶非易失性存储单元（10）。 覆盖的多晶硅浮栅（26）通过薄氧化物层（34）与N阱分离。 P型扩散区（36）形成在浮置栅极（26）下面的N阱的一部分中，由此电容耦合到浮置栅极（26）。 该P型扩散区域用作电池的控制栅极。 通过经由控制栅极（36）将足够的电压耦合到浮置栅极（26），同时偏置源极（20）和漏极（22）区域以便引起来自P +漏极区域（22）的电子的隧穿 ）到浮动栅极（26）。 在一些实施例中，浮动栅极下方并由隧道氧化物层分离的附加P型扩散区域用作存储器单元的擦除栅极。 在这样的实施例中，通过使电子从浮动栅极到擦除栅极隧穿来实现单元的擦除。

公开(公告)号：EP0774788A1

公开(公告)日：1997-05-21

申请号：EP96307875.3

申请日：1996-10-30

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De T.

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/7881 ,  H01L29/7887

摘要： A P-channel flash EEPROM cell (40) has P+ source (50) and P+ drain (52) regions, and a channel (51) extending therebetween, formed in an N-type well (42). A thin layer of tunnel oxide (62) is provided over the channel (51). A poly-silicon floating gate (56) and poly-silicon control gate (58), separated by a dielectric layer (57), overlie the tunnel oxide (62). Programming is accomplished via hot electron injection while erasing is realized by electron tunneling. The threshold voltage of the cell may be precisely controlled by the magnitude of voltage coupled to the floating gate (56) during programming. Since the injection of hot electrons into the floating gate (56) is independent of variations in the thickness of the tunnel oxide layer (62) and the coupling ratio between the floating gate (56) and the control gate (58), programming operations and data retention are not affected by process variations. In addition, PMOS devices conduct a gate current via hot electron injection over a narrow range of gate voltages, thereby allowing for precise control over the gate current and thus over the charging of the floating gate. This control over the gate current, as well as the independence of the cell's threshold voltage of process parameters, advantageously allows the threshold voltage of the cell to be more accurately controlled, thereby resulting in a more reliable cell capable of storing a greater number of bits of data.

摘要翻译： P沟道快闪EEPROM单元（40）具有P +源极（50）和P +漏极（52）区域，以及在N型阱（42）中形成的沟道（51）。 隧道氧化物（62）的薄层设置在通道（51）上。 由电介质层（57）分开的多硅浮动栅极（56）和多晶硅控制栅极（58）覆盖隧道氧化物（62）。 通过电子注入实现编程，同时通过电子隧道实现擦除。 可以通过在编程期间耦合到浮动栅极（56）的电压的大小精确地控制单元的阈值电压。 由于将热电子注入到浮动栅极（56）中是独立于隧道氧化物层（62）的厚度变化和浮动栅极（56）与控制栅极（58）之间的耦合比，编程操作和 数据保留不受流程变化的影响。 此外，PMOS器件通过在窄电压栅极电压下的热电子注入导通栅极电流，从而允许对栅极电流进行精确控制，从而允许对浮栅的充电进行精确控制。 对栅极电流的这种控制以及电池的工艺参数的阈值电压的独立性有利地允许更精确地控制电池的阈值电压，从而导致更可靠的电池能够存储更多数量的电位 数据的。