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公开(公告)号：EP0929900B1
公开(公告)日：2001-11-28
申请号：EP97945360.2
申请日：1997-09-29
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： WENDELL, Dennis, L.
CPC classification number: G11C29/026 , G06F12/1054 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.
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2.发明公开
公开(公告)号：EP0929901A1
公开(公告)日：1999-07-21
申请号：EP97945392.0
申请日：1997-09-29
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： WENDELL, Dennis, L.
CPC classification number: G11C29/026 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.
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3.发明授权
公开(公告)号：EP0929901B1
公开(公告)日：2001-11-28
申请号：EP97945392.5
申请日：1997-09-29
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： WENDELL, Dennis, L.
CPC classification number: G11C29/026 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.
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公开(公告)号：EP0929900A1
公开(公告)日：1999-07-21
申请号：EP97945360.0
申请日：1997-09-29
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： WENDELL, Dennis, L.
CPC classification number: G11C29/026 , G06F12/1054 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.
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