摘要:
A dual-die integrated circuit package (10) having two integrated circuit chips (14, 16) 'flip chip' attached to each other and with one of the chips (14) being aligned at a specified angle in relation to the other chip (16) to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip. Also, being able to use two chips that are identically constructed from a wafer fabrication standpoint provides the advantage of requiring only one IC design process.
摘要:
A device (100) for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device (100) has a substrate (111) with a plurality of substantially concentric electrically-conductive paths (101, 103, 105, 107), each of the plurality of electrically-conductive paths (101, 103, 105, 107) being electrically isolated from each other and formed on a first surface of the substrate (111). At least one (107) of the plurality of electrically-conductive paths (101, 103, 105, 107) is arranged concentrically so as to substantially span a width of the first surface of the substrate (111). A plurality of bonding pads (109) is electrically coupled to each of the electricallyconductive paths (101, 103, 105, 107). The plurality of bonding pads is coupled to one of the electrically conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path (101, 103, 105, 107). The entire interconnect device (100) may be mounted in a standard leadframe product.
摘要:
A redistribution metallization scheme combines solder bumps (122) and wire bond pads (132) in addition to existing bond pads (102) to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals (204, 206, 208) used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.