公开(公告)号：EP4415038A1

公开(公告)日：2024-08-14

申请号：EP23155583.0

申请日：2023-02-08

申请人： Siemens Aktiengesellschaft

发明人： Hensler, Alexander ,  Pfefferlein, Stefan ,  Strogies, Jörg ,  Woiton, Michael ,  Bigl, Thomas ,  Heimann, Matthias ,  Müller, Bernd ,  Wilke, Klaus

IPC分类号： H01L23/373 ,  H05K1/02 ,  H01L29/16

CPC分类号： H01L23/3732 ,  H01L23/3735 ,  H05K1/0201 ,  H05K1/0212 ,  H01L29/1608 ,  H01L29/16 ,  H01L23/367 ,  H01L23/49833

摘要： Es wird eine Schaltungsanordnung mit einem Halbleiterbauelement angegeben, die wenigstens ein Wärmeleitelement mit einer spezifischen Wärmeleitfähigkeit von wenigstens 20 W/mK aufweist, das das Halbleiterbauelement lateral zu wenigstens 50% umschließt und in mechanischem Kontakt mit den Seitenflächen des Halbleiterbauelements steht und wenigstens die halbe Höhe des Halbleiterbauelements aufweist.

公开(公告)号：EP3410483A1

公开(公告)日：2018-12-05

申请号：EP18175313.8

申请日：2018-05-31

申请人： FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V.

发明人： Böttcher, Mathias ,  Wolf, M. Jürgen

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/98 ,  H01L25/10

CPC分类号： H01L25/065 ,  H01L21/568 ,  H01L23/49833 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/1533 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85

摘要： Die Anmeldung betrifft ein Verfahren zur Herstellung eines Packages (1). Bei dem vorgeschlagenen Verfahren werden zunächst eine erste Bauteilanordnung (2) und eine zweite Bauteilanordnung (13) bereitgestellt. Die erste Bauteilanordnung (2) und die zweite Bauteilanordnung (13) weisen jeweils eine flächige Umverdrahtungslage (6, 16) und jeweils zumindest eine auf einer in Richtung einer Vorderseite der Bauteilanordnung (2, 13) weisenden Seite der Umverdrahtungslage (6, 16) angeordnete elektronische Komponente auf (11, 11', 17). Die Umverdrahtungslage (6, 16) weist elektrisch isolierendes Material (8) und Leiterbahnen (9, 9') auf. Zumindest eine der Leiterbahnen (9, 9') der Umverdrahtungslage (6, 16) ist mit der elektronischen Komponente (11, 11', 17) elektrisch leitend verbunden. In einem weiteren Schritt werden die Bauteilanordnungen (2, 13) derart zueinander angeordnet, dass die Vorderseiten der Bauteilanordnungen (2, 13) einander zugewandt sind und dass ein durch die Bauteilanordnungen (2, 13) begrenzter Zwischenraum (21) zwischen den Umverdrahtungslagen (6, 16) ausgebildet wird. In typischen Ausführungen wird ein Füllmaterial in den Zwischenraum eingebracht.

公开(公告)号：EP3240015A4

公开(公告)日：2018-08-01

申请号：EP15872415

申请日：2015-10-07

申请人： MITSUBISHI HEAVY IND MACHINE TOOL CO LTD

发明人： UTSUMI JUN ,  GOTO TAKAYUKI ,  SUZUKI TAKENORI ,  IDE KENSUKE

IPC分类号： H01L21/02 ,  B23K20/00 ,  B23K20/02 ,  B23K20/22 ,  B32B37/14 ,  B81C3/00 ,  H01L21/18 ,  H01L21/20 ,  H01L23/498

CPC分类号： B23K20/02 ,  B23K20/00 ,  B23K20/22 ,  B32B37/14 ,  B81C3/001 ,  H01L21/02 ,  H01L21/187 ,  H01L21/2007 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05572 ,  H01L2224/80895 ,  H01L2924/0002 ,  H01L2924/15787

摘要： Provided is a semiconductor device formed by performing bonding at room temperature with respect to a wafer in which bonded electrodes 23 and 26 and insulating layers 22 and 25 are respectively exposed to front surfaces 17A and 18A, including a bonding interlayer 30 which independently exhibits non-conductivity and exhibits conductivity by being bonded to the bonded electrodes 23 and 26, between the front surfaces 17A and 18A.

公开(公告)号：EP3314648A1

公开(公告)日：2018-05-02

申请号：EP15896530.1

申请日：2015-06-25

申请人： Intel Corporation

发明人： LEE, Kyu-Oh ,  SALAMA, Islam, A.

IPC分类号： H01L25/065 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6666 ,  H01L2224/16157 ,  H01L2224/16197 ,  H01L2224/16225 ,  H01L2924/1205 ,  H01L2924/15311

摘要： Disclosed herein are integrated circuit (IC) structures having interposers with recesses. For example, an IC structure may include: an interposer having a resist surface; a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; and a plurality of conductive contacts located at the resist surface. Other embodiments may be disclosed and/or claimed.

公开(公告)号：EP3309828A2

公开(公告)日：2018-04-18

申请号：EP17190758.7

申请日：2017-09-13

申请人： Renesas Electronics Corporation

发明人： BETSUI, Takafumi

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/50

CPC分类号： H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

摘要： The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor device includes a semiconductor integrated circuit and a substrate. The semiconductor integrated circuit is, for example, a semiconductor chip. The coefficient of thermal expansion is different between the semiconductor integrated circuit and the substrate. The substrate includes a plurality of soldering balls on the opposite surface to the surface where the semiconductor integrated circuit is mounted. The substrate does not have the soldering balls at a position corresponding to at least one side of the fringe of the semiconductor integrated circuit.

摘要翻译： 目的在于当重复从高温到低温的气氛时抑制焊球的破裂。 一种半导体器件包括半导体集成电路和衬底。 半导体集成电路例如是半导体芯片。 半导体集成电路和衬底之间的热膨胀系数不同。 基板在与安装半导体集成电路的表面相对的表面上包括多个焊球。 衬底在与半导体集成电路的边缘的至少一侧相对应的位置处不具有焊球。

公开(公告)号：EP3127149A4

公开(公告)日：2017-09-20

申请号：EP15772304

申请日：2015-03-31

申请人： MICRON TECHNOLOGY INC

发明人： LI JIAN ,  GROOTHUIS STEVEN K

IPC分类号： H01L23/12 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L25/0657 ,  G11C7/04 ,  G11C2207/107 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H01L2924/16787 ,  H01L2924/01047

公开(公告)号：EP3171403A3

公开(公告)日：2017-09-13

申请号：EP16196814.4

申请日：2016-11-02

申请人： MediaTek Inc.

发明人： LIN, Tzu-Hung ,  PENG, I-Hsuan ,  LIU, Nai-Wei ,  HUANG, Wei-Che ,  CHOU, Che-Ya

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L23/66 ,  H01L21/60 ,  H01L25/10

CPC分类号： H01L24/19 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/37001 ,  H01L2924/01029

摘要： The invention provides a semiconductor package assembly (500g, 500h). The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (400) (RDL) structure having a first surface (401) and a second surface (403) opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces (402) close to the first surface of the first RDL structure. An antenna pattern (404) is disposed close to the second surface of the first RDL structure. A first semiconductor die (410) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures (226) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

公开(公告)号：EP3100302A4

公开(公告)日：2017-09-13

申请号：EP14889592

申请日：2014-04-18

申请人： HALLIBURTON ENERGY SERVICES INC

发明人： BONDARENKO OLEG

IPC分类号： H01L23/48 ,  H01L23/34

CPC分类号： H01L23/49838 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49861 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3426 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls to a circuit board, the adapter having an adapter substrate made from a material having substantially the same coefficient of thermal expansion as the substrate used in the chip and having at least one electrical contact site on a mounting surface of the adapter substrate for engaging a solder ball on the ball grid array chip and a plurality of lead wires extending from each side of the adapter substrate. At least one of the lead wires is electrically connected to at least one electrical contact site on the adapter substrate.

摘要翻译： 用于将球栅阵列芯片附接到电路板的示例性方法包括提供用于将具有多个焊球的芯片附接到电路板的适配器，该适配器具有由具有基本上相同的热系数 作为芯片中使用的衬底扩展，并且在适配器衬底的安装表面上具有至少一个电接触部位，用于接合球栅阵列芯片上的焊球以及从适配器衬底的每侧延伸的多条引线。 至少一根引线电连接到适配器基板上的至少一个电接触部位。

公开(公告)号：EP3171403A2

公开(公告)日：2017-05-24

申请号：EP16196814.4

申请日：2016-11-02

申请人： MediaTek Inc.

发明人： LIN, Tzu-Hung ,  PENG, I-Hsuan ,  LIU, Nai-Wei ,  HUANG, Wei-Che ,  CHOU, Che-Ya

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L23/66 ,  H01L21/60 ,  H01L25/10

CPC分类号： H01L24/19 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/37001 ,  H01L2924/01029

摘要： The invention provides a semiconductor package assembly (500g, 500h). The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (400) (RDL) structure having a first surface (401) and a second surface (403) opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces (402) close to the first surface of the first RDL structure. An antenna pattern (404) is disposed close to the second surface of the first RDL structure. A first semiconductor die (410) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures (226) is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

摘要翻译： 本发明提供了一种半导体封装组件（500g，500h）。 半导体封装组件包括第一半导体封装，该第一半导体封装包括具有第一表面（401）和与第一衬底相对的第二表面（403）的第一重新分布层（400）（RDL）结构。 第一RDL结构包括靠近第一RDL结构的第一表面的多个第一导电迹线（402）。 天线图案（404）靠近第一RDL结构的第二表面布置。 第一半导体管芯（410）设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构（226）设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构通过第一RDL结构的多个第一导电迹线与天线图案间隔开。

公开(公告)号：EP1333491B1

公开(公告)日：2017-04-26

申请号：EP03001959.0

申请日：2003-01-30

申请人： Broadcom Corporation

发明人： Khan, Reza-ur Rahman ,  Zhao, Sam Ziqun

IPC分类号： H01L23/36

CPC分类号： H01L23/3735 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/182 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012