公开(公告)号：EP1262996A4

公开(公告)日：2007-06-27

申请号：EP01904349

申请日：2001-02-08

申请人： HITACHI LTD

发明人： ISHIBASHI KOICHIRO ,  SYUKURI SHOJI ,  YANAGISAWA KAZUMASA ,  NISHIMOTO JUNICHI ,  YAMAOKA MASANAO ,  AOKI MASAKAZU

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/42 ,  H01L21/66 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0441 ,  B82Y10/00 ,  C04B28/02 ,  C04B2103/0097 ,  C04B2111/00017 ,  C04B2111/00456 ,  C04B2111/00517 ,  C04B2111/2092 ,  G11C16/04 ,  G11C29/12 ,  G11C29/789 ,  G11C29/848 ,  G11C2216/10 ,  H01L22/22 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/10897 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  C04B14/04 ,  C04B14/06 ,  C04B14/14 ,  C04B14/16 ,  C04B20/008 ,  C04B24/00 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor integrated circuit having multilevel interconnection and copper interconnection. The cost of defect remedy of the circuit and the cost of trimming are reduced. Addresses for remedying a defect in a memory array in the semiconductor are stored in a nonvolatile memory device where the first polysilicon layer is used as a floating electrode. The nonvolatile memory device is programmed during the test of the semiconductor integrated circuit. No special process is needed to fabricate the nonvolatile memory device. That is, the nonvolatile memory device can be fabricated in the process of fabricating a CMOS device. Because the nonvolatile memory device is programmed during the test, no laser for programming is needed and the time required for the programming is shortened, thereby reducing the testing cost.