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公开(公告)号：EP2895432A2
公开(公告)日：2015-07-22
申请号：EP13763416.8
申请日：2013-09-06
发明人： TANGEMAN, Jean A. , LINDSAY, Craig W. , BUDD, Kenton D. , EVERMAN, Rebecca L. , JACOBS, Jeffry L. , EDWARDS, John S.
IPC分类号： C03C11/00 , E04B7/00 , C03C12/00 , C03B19/06 , C04B14/24 , C04B38/00 , C03C14/00 , C03C17/00
CPC分类号： E04D1/00 , A01N25/12 , B01J21/08 , B01J35/004 , C03B19/06 , C03B19/09 , C03C4/02 , C03C4/082 , C03C4/14 , C03C11/00 , C03C12/00 , C03C14/004 , C03C17/007 , C04B18/026 , C04B20/1055 , C04B2111/00586 , E04D7/005 , E04D2001/005 , C04B14/22 , C04B14/303 , C04B2103/0097 , C04B2103/69 , C04B14/30 , C04B14/305 , C04B20/1051
摘要： Building materials, such as roofing granules, including greater than 50% volume of glass are provided. In an exemplary embodiment, one or more additives including colored pigments, infrared-reflective particles, infrared-absorbing particles, algicidal particles, photocatalytic particles, thermally conductive particles, or electrically conductive particles are incorporated at least partially throughout or onto the granule.
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公开(公告)号：EP1262996A1
公开(公告)日：2002-12-04
申请号：EP01904349.6
申请日：2001-02-08
申请人： Hitachi, Ltd.
发明人： ISHIBASHI, Koichiro c/o Hitachi, Ltd. , SYUKURI, Shoji c/o Hitachi, Ltd. , YANAGISAWA, Kazumasa c/o Hitachi, Ltd. , NISHIMOTO, Junichi c/o Hitachi, Ltd. , YAMAOKA, Masanao c/o Hitachi, Ltd. , AOKI, Masakazu c/o Hitachi, Ltd.
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
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公开(公告)号：EP3385239A1
公开(公告)日：2018-10-10
申请号：EP17164720.9
申请日：2017-04-04
申请人： Uzin Utz AG
发明人： WILDE, Markus , GRETZ, Markus , TSALOS, Johannis
CPC分类号： C04B16/00 , C04B24/06 , C04B24/128 , C04B28/02 , C04B28/14 , C04B2103/0097 , C04B2111/60 , C04B2111/62 , C04B2111/807 , C09K11/025 , C09K11/06 , C09K2211/1018 , C04B40/0096
摘要： Die vorliegende Erfindung betrifft mit Wasser anmischbare Fußbodenspachtelmassen umfassend Fluorescein oder ein Derivat hiervon. Die vorliegende Erfindung betrifft darüber hinaus die Verwendung von Fluorescein oder Fluoresceinderivaten als Indikator für die Belegreife einer mit Wasser angemischten Fußbodenspachtelmasse.
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公开(公告)号：EP1262996B1
公开(公告)日：2010-12-15
申请号：EP01904349.6
申请日：2001-02-08
申请人： Hitachi, Ltd.
发明人： ISHIBASHI, Koichiro c/o Hitachi, Ltd. , SYUKURI, Shoji c/o Hitachi, Ltd. , YANAGISAWA, Kazumasa c/o Hitachi, Ltd. , NISHIMOTO, Junichi c/o Hitachi, Ltd. , YAMAOKA, Masanao c/o Hitachi, Ltd. , AOKI, Masakazu c/o Hitachi, Ltd.
IPC分类号： G11C29/00 , H01L21/8247
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor integrated circuit having multilevel interconnection and copper interconnection. The cost of defect remedy of the circuit and the cost of trimming are reduced. Addresses for remedying a defect in a memory array in the semiconductor are stored in a nonvolatile memory device where the first polysilicon layer is used as a floating electrode. The nonvolatile memory device is programmed during the test of the semiconductor integrated circuit. No special process is needed to fabricate the nonvolatile memory device. That is, the nonvolatile memory device can be fabricated in the process of fabricating a CMOS device. Because the nonvolatile memory device is programmed during the test, no laser for programming is needed and the time required for the programming is shortened, thereby reducing the testing cost.
摘要翻译： 为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件通过第一（第一）存储来存储半导体中存储单元阵列的缺陷的地址 多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。 结果，在形成非易失性存储元件时不需要特殊的处理。 换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。 因此，可以缩短编程所需的时间，因此可以降低测试成本。
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公开(公告)号：EP1262996A4
公开(公告)日：2007-06-27
申请号：EP01904349
申请日：2001-02-08
申请人： HITACHI LTD
发明人： ISHIBASHI KOICHIRO , SYUKURI SHOJI , YANAGISAWA KAZUMASA , NISHIMOTO JUNICHI , YAMAOKA MASANAO , AOKI MASAKAZU
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor integrated circuit having multilevel interconnection and copper interconnection. The cost of defect remedy of the circuit and the cost of trimming are reduced. Addresses for remedying a defect in a memory array in the semiconductor are stored in a nonvolatile memory device where the first polysilicon layer is used as a floating electrode. The nonvolatile memory device is programmed during the test of the semiconductor integrated circuit. No special process is needed to fabricate the nonvolatile memory device. That is, the nonvolatile memory device can be fabricated in the process of fabricating a CMOS device. Because the nonvolatile memory device is programmed during the test, no laser for programming is needed and the time required for the programming is shortened, thereby reducing the testing cost.
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