公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1875507A4

公开(公告)日：2009-08-05

申请号：EP06740000

申请日：2006-03-30

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：EP1794786A4

公开(公告)日：2008-12-24

申请号：EP05785191

申请日：2005-06-21

Applicant: IBM

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了一种用于导电载体的结构和形成方法，该结构包括在<110>中具有上表面的Si或SiGe的单晶衬底以及具有不同于衬底的Ge浓度的伪晶体或外延层，由此该伪晶体层 正处于紧张状态。 描述了用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中形成假性或外延层的步骤，通过将工具中的温度提高至约600℃并且将含Si气体和Ge 含有气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底分别浸入一系列含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，接着在惰性气氛中干燥衬底 以获得无杂质且具有小于0.1nm的RMS粗糙度的基材表面。