公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP1790003A4

公开(公告)日：2011-01-12

申请号：EP05784302

申请日：2005-08-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP2588650A4

公开(公告)日：2014-03-19

申请号：EP11801264

申请日：2011-06-23

Applicant: MATHESON TRI GAS INC ,  IBM

Inventor： FRANCIS TERRY ARTHUR ,  HASAKA SATOSHI ,  BRABANT PAUL DAVID ,  TORRES ROBERT JR ,  HE HONG ,  REZNICEK ALEXANDER ,  ADAM THOMAS N ,  SADANA DEVENDRA K

IPC: C30B25/02 ,  C23C16/30 ,  C23C16/32 ,  C30B29/06 ,  H01L21/02

CPC classification number: H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

公开(公告)号：EP1709671A4

公开(公告)日：2010-06-16

申请号：EP04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  MOCUTA DAN M

IPC: H01L21/331 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.