公开(公告)号：EP3182461A1

公开(公告)日：2017-06-21

申请号：EP15200415.6

申请日：2015-12-16

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： HELLINGS, Geert ,  BOSCHKE, Roman ,  LINTEN, Dimitri ,  HORIGUCHI, Naoto

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： The present invention relates to a semiconductor fin device (100) comprising at least three fins (102-106) arranged in parallel and protruding out from a substrate (111), the fins are separated from each other by shallow trench isolation structures (101), at least a first (102) and a second (106) of the fins protruding to a level higher than an upper surface (107) of the shallow trench isolation structures, the parallel fins are spaced with a first fin spacing (108), with at least one third fin arranged in between a first and a second fin, wherein in a non-protruding region (110) the third fin extends to a level below or equal to the upper surface of the shallow trench isolation structures.

摘要翻译： 本发明涉及一种包括至少三个平行排列并从衬底（111）突出的鳍（102-106）的半导体鳍式器件（100），所述鳍通过浅沟槽隔离结构（101）彼此分离， ，所述鳍片中的至少第一（102）和第二（106）突出到比所述浅沟槽隔离结构的上表面（107）高的水平，所述平行鳍片以第一鳍片间隔（108）隔开， 其中至少一个第三鳍片被布置在第一鳍片与第二鳍片之间，其中在非突出区域（110）中，第三鳍片延伸至低于或等于浅沟槽隔离结构的上表面的水平。

公开(公告)号：EP3270539A1

公开(公告)日：2018-01-17

申请号：EP17180190.5

申请日：2017-07-07

申请人： IMEC vzw ,  Katholieke Universiteit Leuven

发明人： BURY, Erik ,  FRANCO, Jacopo ,  HELLINGS, Geert ,  DEGRAEVE, Robin ,  KACZER, Benjamin

IPC分类号： H04L9/32 ,  H04L9/08 ,  G09C1/00

CPC分类号： H03K19/003 ,  G09C1/00 ,  H01L21/326 ,  H01L23/528 ,  H01L23/573 ,  H01L27/0203 ,  H01L27/088 ,  H03K17/002 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278

摘要： Present invention relates to a device (100), and related systems and methods, for implementing a physically unclonable function. The device comprises at least one electronic structure (101,102) comprising a dielectric (105). A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric (105), or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that said conductive path is formed through the dielectric (105) at a random position. The at least one electronic structure is furthermore adapted for determining a distinct value of a set comprising at least two predetermined values, wherein this distinct value is determined by the position of the conductive path through the dielectric (105).

摘要翻译： 本发明涉及用于实现物理不可克隆功能的设备（100）以及相关系统和方法。 该装置包括至少一个包括电介质（105）的电子结构（101,102）。 由于电介质（105）的电击穿，导电路径形成在通过电介质的随机位置处，或者电子结构适于产生电介质的电击穿，使得所述导电路径穿过电介质（105 ）在随机位置。 所述至少一个电子结构还适于确定包括至少两个预定值的组的不同值，其中该不同值由通过电介质（105）的导电路径的位置确定。

公开(公告)号：EP3188248A1

公开(公告)日：2017-07-05

申请号：EP15203221.5

申请日：2015-12-30

申请人： IMEC VZW

发明人： CHEN, Shih-Hung ,  LINTEN, Dimitri ,  HELLINGS, Geert

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7835 ,  H01L29/7851

摘要： An LDMOS device (300) in FinFET technology comprises a first region (210) substantially surrounded by a second region (220) of different polarity; a first fin (330) in the first region (210), extends into the second region (220), and comprises a doped source region (410) connected with a first local interconnect (380); a second fin (340) in the second region (220), comprises a doped drain region (420) connected with a second local interconnect (382); a third fin (350) parallel with the first and second fin (330) comprises a doped drain region connected with the second local interconnect (382); a gate (360) over the first fin (330) at the border between the first and second regions. In operation a first current path runs over the first and second fins (330, 340), and a second current path runs over the first fin (330) and perpendicular from the first fin towards the third fin (350).

摘要翻译： FinFET技术中的LDMOS器件（300）包括基本上由不同极性的第二区域（220）围绕的第一区域（210） 所述第一区域（210）中的第一鳍状物（330）延伸到所述第二区域（220）中，并且包括与第一局部互连（380）连接的掺杂源极区域（410）; 所述第二区域（220）中的第二鳍（340）包括与第二局部互连（382）连接的掺杂漏极区（420）; 与第一和第二鳍片330平行的第三鳍片350包括与第二局部互连382连接的掺杂漏极区域; 在第一和第二区域之间的边界处的第一鳍状物（330）之上的栅极（360）。 在操作中，第一电流路径在第一鳍状物和第二鳍状物（330,340）上方延伸，并且第二电流路径在第一鳍状物（330）上方并且垂直于第一鳍状物朝向第三鳍状物（350）延伸。

公开(公告)号：EP3188248B1

公开(公告)日：2018-11-28

申请号：EP15203221.5

申请日：2015-12-30

申请人： IMEC VZW

发明人： CHEN, Shih-Hung ,  LINTEN, Dimitri ,  HELLINGS, Geert

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7835 ,  H01L29/7851

摘要： An LDMOS device (300) in FinFET technology comprises a first region (210) substantially surrounded by a second region (220) of different polarity; a first fin (330) in the first region (210), extends into the second region (220), and comprises a doped source region (410) connected with a first local interconnect (380); a second fin (340) in the second region (220), comprises a doped drain region (420) connected with a second local interconnect (382); a third fin (350) parallel with the first and second fin (330) comprises a doped drain region connected with the second local interconnect (382); a gate (360) over the first fin (330) at the border between the first and second regions. In operation a first current path runs over the first and second fins (330, 340), and a second current path runs over the first fin (330) and perpendicular from the first fin towards the third fin (350).

公开(公告)号：EP3340308A1

公开(公告)日：2018-06-27

申请号：EP16206087.5

申请日：2016-12-22

申请人： IMEC vzw

发明人： HELLINGS, Geert

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/42392 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7851

摘要： According to an aspect of the present inventive concept there is provided a method for forming a gate all around field effect transistor (136), GAAFET, in a first region (104) of a substrate (101) and a fin field effect transistor (138), finFET, in a second region (106) of the substrate (101), the first region (104) including a first semiconductor feature (108) and the second region including a second semiconductor feature (110), each of said semiconductor features (108, 110) being a fin-shaped semiconductor feature (108, 110) including a vertical stack (150) of at least a first semiconductor material layer (152a, 152b) and a second semiconductor material layer (154a, 154b) arranged above the first semiconductor material layer (152a, 152b), the method comprising:
selectively removing the first semiconductor material (152a, 152b) from a longitudinal section of the first semiconductor feature (108) by etching to form a suspended longitudinal first semiconductor feature (154a, 154b) of the remaining second semiconductor material (154a, 154b), while masking the second region (106) to counteract etching of the second semiconductor feature (110), and
forming a gate all around electrode (132) on the suspended longitudinal first semiconductor feature (154a, 154b) in the first region (104) and a gate electrode (130) on the fin-shaped second semiconductor feature (110) in the second region (106).

公开(公告)号：EP4396869A1

公开(公告)日：2024-07-10

申请号：EP21773062.1

申请日：2021-09-03

申请人： IMEC VZW ,  Huawei Technologies Co., Ltd.

发明人： RAWAT, Amita ,  WU, Hao ,  HELLINGS, Geert ,  BHUWALKA, Krishna Kumar

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/775

CPC分类号： H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/775 ,  H01L29/0673 ,  B82Y10/00

公开(公告)号：EP3671858A1

公开(公告)日：2020-06-24

申请号：EP18214421.2

申请日：2018-12-20

申请人： IMEC vzw

发明人： HELLINGS, Geert ,  CHEN, Shih-Hung ,  LINTEN, Dimitri

IPC分类号： H01L29/78 ,  H01L29/423

摘要： A field-effect transistor device (100) is disclosed, comprising a source-side region (110) of a first conductivity type and a source (112) of a second conductivity type formed in the source-side region. The device further comprises a drain-side region (120) of the second conductivity type and a drain (122) of the second conductivity type formed in the drain-side region. A gate structure (130) is adapted to control a flow of current through a channel (140) between the source and the drain, and comprises a first gate electrode (132) arranged along and coupled to a first channel portion (142) in the source-side region, and a second gate electrode (134) arranged in a trench (124) in the drain-side region and coupled to a second channel portion (144) in the drain-side region.

公开(公告)号：EP3620783A1

公开(公告)日：2020-03-11

申请号：EP18192768.2

申请日：2018-09-05

申请人： IMEC vzw

发明人： HELLINGS, Geert ,  MARTENS, Koen

IPC分类号： G01N27/414 ,  H01L29/10

摘要： A sensor comprising a field effect transistor comprising:
• an active region comprising:
∘ a source region and a drain region defining a source-drain axis,
∘ a channel region between the source region and the drain region,

• a dielectric region on the channel region, comprising at least a first zone on a first portion of the channel region and a second zone on a second portion of the channel region, the first zone measuring from 1 to 100 nm in the direction of the source-drain axis and being adapted to create a different threshold voltage for the first portion of the channel region than for the second portion of the channel region, and
• a fluidic gate region to which a top surface of the dielectric region is exposed. A biosensing device comprising such a sensor; a method for using such a sensor; and a process for making such a sensor.