公开(公告)号：EP4294161A1

公开(公告)日：2023-12-20

申请号：EP23173771.9

申请日：2023-05-16

申请人： INTEL Corporation

发明人： LIN, Chia-Ching ,  CHANG, Sou-Chi ,  OGUZ, Kaan ,  SEN GUPTA, Arnab ,  TUNG, I-Cheng ,  LEE, Sudarat ,  METZ, Matthew V. ,  CLENDENNING, Scott B. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

IPC分类号： H10N97/00

摘要： Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

公开(公告)号：EP2761663B1

公开(公告)日：2016-09-14

申请号：EP11873468.0

申请日：2011-09-29

申请人： Intel Corporation

发明人： ROMERO, Patricio E. ,  CLENDENNING, Scott B.

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L29/78 ,  H01L21/336 ,  C23C16/30 ,  C23C16/42 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC分类号： H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP4202990A1

公开(公告)日：2023-06-28

申请号：EP22207204.3

申请日：2022-11-14

申请人： INTEL Corporation

发明人： PLOMBON, John ,  RESHOTKO, Miriam ,  KOBRINSKY, Mauro ,  JEZEWSKI, Christopher ,  CLENDENNING, Scott B. ,  CHEN, Jiun-Ruey

IPC分类号： H01L21/768

摘要： Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

公开(公告)号：EP4156303A1

公开(公告)日：2023-03-29

申请号：EP22197324.1

申请日：2022-09-23

申请人： INTEL Corporation

发明人： LEE, Sudarat ,  DOROW, Chelsey ,  OBRIEN, Kevin ,  NAYLOR, Carl ,  MAXEY, Kirby ,  MOKHTARZADEH, Charles ,  PENUMATCHA, Ashish Verma ,  CLENDENNING, Scott B. ,  AVCI, Uygar E.

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/778

摘要： Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.

公开(公告)号：EP4156299A1

公开(公告)日：2023-03-29

申请号：EP22197316.7

申请日：2022-09-23

申请人： INTEL Corporation

发明人： NAYLOR, Carl ,  MAXEY, Kirby ,  OBRIEN, Kevin ,  DOROW, Chelsey ,  LEE, Sudarat ,  PENUMATCHA, Ashish Verma ,  AVCI, Uygar E. ,  METZ, Matthew ,  CLENDENNING, Scott B.

IPC分类号： H01L29/778 ,  H01L29/267 ,  H01L29/786

摘要： Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

公开(公告)号：EP3198652A1

公开(公告)日：2017-08-02

申请号：EP14902843.3

申请日：2014-09-26

申请人： INTEL Corporation

发明人： CLENDENNING, Scott B. ,  LIAO, Szuya S. ,  GSTREIN, Florian ,  HOURANI, Rami ,  ROMERO, Patricio E. ,  KLOSTER, Grant M. ,  MITAN, Martin M.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0673 ,  H01L21/265 ,  H01L21/28247 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

摘要翻译： 讨论了与用于形成用于半导体器件的选择性栅极隔离物和使用这种技术形成的晶体管结构和器件有关的技术。 这种技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同表面化学性质的栅极，在栅极上而不是在阻挡材料的一部分上形成选择性共形层， 并去除阻挡材料的暴露部分。

公开(公告)号：EP3314635A1

公开(公告)日：2018-05-02

申请号：EP15897299.2

申请日：2015-06-27

申请人： INTEL Corporation

发明人： CHU-KUNG, Benjamin ,  LE, Van H. ,  RIOS, Rafael ,  DEWEY, Gilbert ,  CLENDENNING, Scott B. ,  KAVALIEROS, Jack T.

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

摘要： An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：EP3155655A1

公开(公告)日：2017-04-19

申请号：EP14895432.4

申请日：2014-06-16

申请人： Intel Corporation

发明人： ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  JEZEWSKI, Christopher J. ,  CHEBIAM , Ramanan V.

IPC分类号： H01L21/38 ,  H01L21/31 ,  H01L21/205

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10734 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了集成电路（IC）设备的金属与相关联的技术和配置之间的选择性扩散阻挡层。 在一个实施例中，一种装置包括电介质材料，第一互连结构，包括布置在电介质材料中的第一金属，第二互连结构，包括设置在电介质材料中并与第一互连结构电耦合的第二金属和扩散阻挡层 设置在所述第一互连结构和所述第二互连结构之间的界面处，其中所述第一金属和所述第二金属具有不同的化学组成，所述扩散阻挡层和所述第二金属的材料具有不同的化学组成，并且所述扩散阻挡层的材料为 不直接设置在第二金属和电介质材料之间。 可以描述和/或要求保护其他实施例。

公开(公告)号：EP2761663A1

公开(公告)日：2014-08-06

申请号：EP11873468.0

申请日：2011-09-29

申请人： Intel Corporation

发明人： ROMERO, Patricio E. ,  CLENDENNING, Scott B.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

公开(公告)号：EP4202992A1

公开(公告)日：2023-06-28

申请号：EP22214360.4

申请日：2022-12-16

申请人： INTEL Corporation

发明人： KARPOV, Elijah ,  RESHOTKO, Miriam ,  CLENDENNING, Scott B. ,  CHEN, Jiun-Ruey ,  METZ, Matthew

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.