公开(公告)号：EP3479411A1

公开(公告)日：2019-05-08

申请号：EP16907603.1

申请日：2016-07-01

申请人： INTEL Corporation

发明人： GLASS, Glenn A. ,  MURTHY, Anand S. ,  JAMBUNATHAN, Karthik ,  MOHAPATRA, Chandra S. ,  KOBRINSKY, Mauro J. ,  MORROW, Patrick

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234

公开(公告)号：EP3308403A1

公开(公告)日：2018-04-18

申请号：EP15895116.0

申请日：2015-06-12

申请人： Intel Corporation

发明人： GLASS, Glenn A. ,  MURTHY, Anand S. ,  KAM, Hei ,  GHANI, Tahir ,  JAMBUNATHAN, Karthik ,  MOHAPATRA, Chandra S.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6681 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

摘要： Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

公开(公告)号：EP3238264A1

公开(公告)日：2017-11-01

申请号：EP14909221.5

申请日：2014-12-23

申请人： Intel Corporation

发明人： RACHMADY, Willy ,  METZ, Matthew V. ,  MOHAPATRA, Chandra S. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia M. ,  GHANI, Tahir ,  GLASS, Glenn A.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/762 ,  H01L27/108 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

摘要： An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.

摘要翻译： 一种包括设置在衬底上的外延子鳍结构，其中，所述子鳍结构的第一部分设置在所述衬底的一部分内，并且所述子鳍结构的第二部分设置为与电介质材料相邻。 鳍式装置结构设置于鳍式结构上，其中鳍式装置结构包括外延材料。 衬垫布置在子鳍状结构的第二部分和电介质材料之间。 这里描述了其他实施例。

公开(公告)号：EP3235007A1

公开(公告)日：2017-10-25

申请号：EP14908566.4

申请日：2014-12-17

申请人： Intel Corporation

发明人： DEWEY, Gilbert ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  RACHMADY, Willy ,  GHANI, Tahir ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S. ,  KENNEL, Harold W. ,  GLASS, Glenn A.

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

摘要： An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种器件，该器件包括：包括掺杂沟槽材料的沟槽，所述掺杂沟槽材料具有：（a）（i）第一体晶格常数和（a）（ii）III-V族材料和IV族材料中的至少一种 ; （b）（ii）第二体晶格常数和（b）（ii）III-V族材料和IV族材料中的至少一种的翅片材料; 在所述沟槽内并直接接触所述鳍状物的底表面的阻挡层，所述阻挡层包括具有第三体晶格常数的阻挡层材料; 其中（a）所述沟槽具有至少1.5:1的纵横比（深度与宽度），并且（b）所述阻挡层具有不高于所述阻挡层材料的临界厚度的高度。 这里描述了其他实施例。

公开(公告)号：EP3087609A1

公开(公告)日：2016-11-02

申请号：EP13900120.0

申请日：2013-12-23

申请人： INTEL Corporation

发明人： GLASS, Glenn A. ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S.

IPC分类号： H01L29/78 ,  H01L21/336

摘要： An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.

摘要翻译： 公开了用于形成这种器件的n-MOS晶体管器件和方法。 该n-MOS晶体管器件包括具有形成在衬底上方的一个或多个置换有源区的半导体衬底。 替代有源区域包括第一III-V族半导体材料。 在替代有源区上方形成栅极结构。 源极/漏极（S / D）凹陷形成在与栅极结构相邻的替代有源区中。 置换S / D区域形成在S / D凹槽中并且包括具有小于第一III-V半导体材料的晶格常数的晶格常数的第二III-V族半导体材料。 第二III-V族材料的较小晶格常数在由第一III-V族材料形成的沟道上引起单轴应变。 沟道中的单轴应变改善了n-MOS器件中的载流子迁移率。

公开(公告)号：EP3437137A1

公开(公告)日：2019-02-06

申请号：EP16897413.7

申请日：2016-04-01

申请人： INTEL Corporation

发明人： MOHAPATRA, Chandra S. ,  GLASS, Glenn A. ,  KENNEL, Harold W. ,  MURTHY, Anand S. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  MA, Sean T. ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

公开(公告)号：EP3314665A1

公开(公告)日：2018-05-02

申请号：EP15896567.3

申请日：2015-06-26

申请人： INTEL Corporation

发明人： RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia M. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/785

摘要： Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：EP3238267A1

公开(公告)日：2017-11-01

申请号：EP14909247.0

申请日：2014-12-23

申请人： Intel Corporation

发明人： GARDNER, Sanaz K. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia ,  ZELICK, Nancy M. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

摘要： An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，该装置包括：包括上部和下部的翅片结构，上部具有与下部的上表面直接接触的底表面; 其中（a）下部包含在具有至少2：1的纵横比（深宽比）的沟槽中; （b）底面具有底部最大宽度，并且上表面具有底部最大宽度更大的上部最大宽度; （c）底面覆盖上表面的中间部分，但不覆盖上表面的侧面部分; （d）上部包括上部III-V族材料，下部包括不同于上部III-V族材料的下部III-V族材料。 这里描述了其他实施例。

公开(公告)号：EP3238262A1

公开(公告)日：2017-11-01

申请号：EP14909194.4

申请日：2014-12-22

申请人： Intel Corporation

发明人： JAMBUNATHAN, Karthik ,  GLASS, Glenn A. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  CEA, Stephen M. ,  GHANI, Tahir

IPC分类号： H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/0607 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and III-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，包括：在衬底上的鳍结构，所述鳍结构包括鳍顶部和底部，包括多数载流子的沟道以及外延（EPI）层; 绝缘层，包括与鳍顶部和底部相邻的绝缘层顶部和底部; 其中（a）所述EPI层包括IV族和III-V族材料中的一种或多种，​​（b）所述翅片底部包括与所述多数载体相反极性的翅片底部浓度的掺杂剂，（c）所述翅片顶部 包括掺杂物的鳍顶部浓度小于鳍底部浓度，（d）绝缘层底部包括掺杂物的绝缘层底部浓度，以及（e）绝缘层顶部包括绝缘顶层 部分浓度大于绝热底部浓度。 这里描述了其他实施例。

公开(公告)号：EP3238242A1

公开(公告)日：2017-11-01

申请号：EP14909265.2

申请日：2014-12-24

申请人： Intel Corporation

发明人： GARDNER, Sanaz K. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia M. ,  ZELICK, Nancy M. ,  GHANI, Tahir

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/785

摘要： Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

摘要翻译： 本发明的实施例包括纳米线和纳米带晶体管以及形成这种晶体管的方法。 根据一个实施例，用于形成微电子器件的方法可以包括在形成于浅沟槽隔离（STI）层中的沟槽内形成多层堆叠。 多层堆叠可以包括至少一个沟道层，在沟道层下方形成的释放层以及在沟道层下方形成的缓冲层。 STI层可以凹入，使得STI层的顶部表面低于释放层的顶部表面。 通过相对于沟道层选择性地蚀刻释放层而从沟道层下方暴露释放层。