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公开(公告)号：EP4248501A1
公开(公告)日：2023-09-27
申请号：EP21815167.8
申请日：2021-11-16
发明人： CHENG, Kangguo , RADENS, Carl , XIE, Ruilong , LI, Juntao
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公开(公告)号：EP2235743A1
公开(公告)日：2010-10-06
申请号：EP09704665.0
申请日：2009-01-15
发明人： DALTON, Timothy , DORIS, Bruce, B. , KIM, Ho-cheol , RADENS, Carl
IPC分类号： H01L21/3213
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.
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3.发明公开STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开具有掩埋硅化垂直晶体管和位与多晶硅线和它们的制备PROCEDURE DRAM存储器装置
公开(公告)号：EP1402576A2
公开(公告)日：2004-03-31
申请号：EP02735647.6
申请日：2002-06-27
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
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4.发明公开
公开(公告)号：EP4420497A1
公开(公告)日：2024-08-28
申请号：EP22799919.0
申请日：2022-10-04
发明人： LI, Juntao , XIE, Ruilong , CHENG, Kangguo , RADENS, Carl
IPC分类号： H10N30/01 , H10N30/074 , H10N30/85 , H10N30/87
CPC分类号： H10N70/231 , H10N70/826 , H10N70/061 , H10N70/011 , H10N70/063
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公开(公告)号：EP2250123A2
公开(公告)日：2010-11-17
申请号：EP09709244.9
申请日：2009-02-03
IPC分类号： B82B3/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, hexagonal tiles encompassing a large are divided into three groups, each containing one-third of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group (01, 02, 03) are formed in a template layer (2OA, 2OB, 20C), and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self- aligned line and space structures (4OA, 5OA; 4OB, 5OB; 4OC, 50C) are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
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6.发明公开
公开(公告)号：EP1911096A2
公开(公告)日：2008-04-16
申请号：EP06788341.3
申请日：2006-07-24
发明人： DALTON, Timothy, J. , HSU, Louis, L.c. , WONG, Keith Kwong Hon , YANG, Chih-chao , GAIDIS, Michael, C. , RADENS, Carl , CLEVENGER, Lawrence, A.
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译： 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆栈，形成在MTJ堆栈上的硬掩模以及形成在硬掩模上的上布线层。 上布线层包括形成于其中的狭缝穿过位线，狭缝经由位线与硬掩模接触并且与部分地围绕硬掩模的侧壁的蚀刻停止层接触。
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公开(公告)号：EP1588403A2
公开(公告)日：2005-10-26
申请号：EP04702490.6
申请日：2004-01-15
IPC分类号： H01L21/00
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).
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公开(公告)号：EP2235743B1
公开(公告)日：2014-12-31
申请号：EP09704665.0
申请日：2009-01-15
发明人： DALTON, Timothy , DORIS, Bruce, B. , KIM, Ho-cheol , RADENS, Carl
IPC分类号： H01L21/033 , B81C1/00
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
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9.发明授权HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权根据上述制造平面磁畴壁与加工高密度存储设备
公开(公告)号：EP2140458B1
公开(公告)日：2011-03-23
申请号：EP07867608.7
申请日：2007-12-04
发明人： GAIDIS, Michael, C. , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , DEBROSSE, John, K. , HSU, Louis, L., C. , RADENS, Carl , WONG, Keith, K., H. , YANG, Chih-Chao
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
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10.发明公开HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权根据上述制造平面磁畴壁与加工高密度存储设备
公开(公告)号：EP2140458A1
公开(公告)日：2010-01-06
申请号：EP07867608.7
申请日：2007-12-04
发明人： GAIDIS, Michael, C. , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , DEBROSSE, John, K. , HSU, Louis, L., C. , RADENS, Carl , WONG, Keith, K., H. , YANG, Chih-Chao
IPC分类号： G11C19/08
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
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