公开(公告)号：EP2064744A2

公开(公告)日：2009-06-03

申请号：EP07820358.5

申请日：2007-09-19

申请人： QuNano AB

发明人： WERNERSSON, Lars-Erik ,  LIND, Erik ,  BRYLLERT, Tomas ,  OHLSSON, Jonas ,  LÖWGREN, Truls ,  SAMUELSON, Lars ,  THELANDER, Claes

IPC分类号： H01L29/06 ,  H01L27/088

CPC分类号： H01L27/0883 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/775 ,  H01L29/7828

摘要： The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

公开(公告)号：EP2095426A2

公开(公告)日：2009-09-02

申请号：EP07861100.1

申请日：2007-12-22

申请人： QuNano AB

发明人： SVENSSON, Patrik ,  OHLSSON, Jonas ,  SAMUELSON, Lars ,  LÖWGREN, Truls ,  MARTYNOV, Yourii

IPC分类号： H01L29/06 ,  B82B1/00 ,  H01L21/205

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/02639 ,  H01L21/02653 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/2003 ,  H01L33/18 ,  H01L33/20 ,  H01L33/24

摘要： The present invention provides a semiconductor device comprising a semiconductor nanoelement (100) and a volume element (105) arranged in epitaxial connection to each other. The semiconductor device is electrically connectable with the volume element (105) and the nanoelement (100) electrically connected in series. The volume element (105) is at least partly doped to provide a high charge carrier concentration into the nanoelement (100) and a low access resistance in an electrical connection to the volume element (105). Preferably the nanoelement (100) protrudes from a semiconductor substrate (110). A concentric layer (106) may be arranged on the volume element (105) to form an electrical contact. LED structures comprising nanoelement-volume element structures (100, 105) are disclosed. A method for producing a semiconductor device according to the invention is also presented.

公开(公告)号：EP2064745A1

公开(公告)日：2009-06-03

申请号：EP07803546.6

申请日：2007-09-18

申请人： QuNano AB

发明人： OHLSSON, Jonas ,  SAMUELSON, Lars ,  LIND, Erik ,  WERNERSSON, Lars-Erik ,  LÖWGREN, Truls

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L33/00 ,  C30B29/60 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7828 ,  H01L29/78642 ,  H01L33/24 ,  Y10S977/888 ,  Y10S977/89

摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilised in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15，20）提供不同厚度的层。 在本发明特别涉及到栅电极和精度层在半导体结构的形成（28）包括（10）和细长结构的基板（5）基本上由基底站立起来。 。根据本发明的方法中的装置（1）被用在结合要么各向异性沉积或各向异性去除沉积的材料来形成的精度非常高的垂直或水平层的垂直几何形状。