公开(公告)号：EP1864317A1

公开(公告)日：2007-12-12

申请号：EP05732769.4

申请日：2005-03-29

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： LETERTRE, Fabrice ,  MAZURE, Carlos

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/2007 ,  H01L21/76254

摘要： The invention proposes a SOI-type multilayer structure (105), comprising a support layer (101), at least two working layers (103, 104) having different crystalline orientations, an insulating layer (102) extending over at least a portion of said support layer (101), characterized in that said insulating layer (102) extends over the whole surface of said support layer (101), so as to extend between said support layer (101) and said working layers (103, 104). A process for manufacturing such a structure (105) is also provided.

公开(公告)号：EP1631983A1

公开(公告)日：2006-03-08

申请号：EP04767237.3

申请日：2004-06-03

申请人： S.O.I.Tec Silicon on Insulator Technologies ,  COMMISSARIAT A L'ENERGIE ATOMIQUE

发明人： GHYSELEN, Bruno ,  AULNETTE, Cécile ,  BATAILLOU, Benoit ,  MAZURE, Carlos ,  MORICEAU, Hubert

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： The invention relates to a method for simultaneously obtaining at least one pair of structures (51, 52) each having a useful layer (110, 120) placed on a substrate (71,2). This method is characterized by comprising the following steps consisting of: a) preparing a row structure (1) having a useful layer placed on a supporting substrate (2); b) forming a fragilization area inside said useful layer whereby defining a front useful layer (110) and a rear useful layer (120); c) adhering a stiffening substrate (71) to said front useful layer (110); d) removing the stack of layers along the fragilization area in order to obtain two row structures (2), the first (51) containing the supporting substrate (2) and the rear useful area (120), and the second (52) containing the stiffening substrate (71) and the front useful layer (110). The invention is for use in the fields of electronics, optoelectronics or optics.

公开(公告)号：EP1597759A1

公开(公告)日：2005-11-23

申请号：EP04715982.7

申请日：2004-03-01

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  MAZURE, Carlos ,  ARENE, Emmanuel

IPC分类号： H01L21/763 ,  H01L21/20

CPC分类号： H01L21/76259 ,  H01L21/76254

摘要： The invention relates to a method for forming a relaxed or pseudo-­relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, comprising the following steps: a) growing on a donor substrate (1) an elastically strained layer (2) constituted by at least a material chosen from among the semiconductor materials; b) forming on the strained layer (2), or on a receiver substrate (7), a vitreous layer (4) made of a material which is viscous above a viscosity temperature of more than about 900°C; c) bonding the receiver substrate (7) to the strained layer (2) by means of the vitreous layer (4) formed in step (b); d) removing the donor substrate (1), so as to form a structure (20) comprising the receiver substrate, the vitreous layer (4) and the strained layer (2); e) thermal treating the structure at a temperature close to or above the viscosity temperature, so as to relax at least a part of the constraints in the strained layer (2).

公开(公告)号：EP2324493A2

公开(公告)日：2011-05-25

申请号：EP09777696.7

申请日：2009-08-06

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： LETERTRE, Fabrice ,  MAZURE, Carlos ,  KRAMES, Michael, R. ,  MCLAURIN, Melvin, B. ,  GARDNER, Nathan, F.

IPC分类号： H01L21/324 ,  H01L21/20 ,  H01L33/00

CPC分类号： H01L21/2007 ,  H01L21/02422 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/3245 ,  H01L33/0095

摘要： The present invention relates to a method for relaxing a strained material layer, comprising depositing a first low-viscosity layer comprising a first compliant material on the strained material layer, depositing a second low-viscosity layer comprising a second compliant material on the strained material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.

公开(公告)号：EP1568073A1

公开(公告)日：2005-08-31

申请号：EP03789590.1

申请日：2003-12-05

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： MAZURE, Carlos

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/76259 ,  H01L21/76254

摘要： The present invention relates to a production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate (20) made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps: -producing a layer (110) comprising said superficial thin layer on a support substrate (100), -creating an embrittlement zone in the ensemble (10) formed by said support substrate and said deposited layer, -bonding said ensemble with a target substrate (20), -detaching at the level of this embrittlement zone, -treating the surface of the resulting structure.

公开(公告)号：EP1468128A2

公开(公告)日：2004-10-20

申请号：EP03702513.7

申请日：2003-01-21

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  LETERTRE, Fabrice ,  MAZURE, Carlos

IPC分类号： C30B29/40 ,  C23C16/27 ,  H01L21/20

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： The invention relates to a method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material.This method is characterized by the following steps comprising: - transferring of a thin nucleation layer (5, 5') onto a support (7) by creating between the two a removable bonding interface (9) ;- growing by epitaxy on said thin nucleation layer (5, 5'), a microcrystalline layer (10) of material intended to comprise said substrate, until it attains a sufficient thickness to be free-standing, while preserving the removable character of the bonding interface (9) ; the coefficients of thermal expansion of the material of the thick layer (10) and of the support material (7) being chosen to be different from each other, such that at the time of cooling of the assembly, the stresses induced by differential thermal expansion between the support material (7) and that of the thick layer (10) causing the removal of said nucleation layer (5, 5') and said monocrystalline thick layer (10) from said support (7) at the level of said removable bonding interface (9).

公开(公告)号：EP1468128B1

公开(公告)日：2011-11-23

申请号：EP03702513.7

申请日：2003-01-21

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： GHYSELEN, Bruno ,  LETERTRE, Fabrice ,  MAZURE, Carlos

IPC分类号： C30B29/40 ,  C23C16/27 ,  H01L21/20

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： The invention relates to a method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material.This method is characterized by the following steps comprising: - transferring of a thin nucleation layer (5, 5') onto a support (7) by creating between the two a removable bonding interface (9) ;- growing by epitaxy on said thin nucleation layer (5, 5'), a microcrystalline layer (10) of material intended to comprise said substrate, until it attains a sufficient thickness to be free-standing, while preserving the removable character of the bonding interface (9) ; the coefficients of thermal expansion of the material of the thick layer (10) and of the support material (7) being chosen to be different from each other, such that at the time of cooling of the assembly, the stresses induced by differential thermal expansion between the support material (7) and that of the thick layer (10) causing the removal of said nucleation layer (5, 5') and said monocrystalline thick layer (10) from said support (7) at the level of said removable bonding interface (9).

公开(公告)号：EP2269226A1

公开(公告)日：2011-01-05

申请号：EP08763204.8

申请日：2008-03-13

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： ALLIBERT, Frédéric ,  GAUDIN, Gweltaz ,  LALLEMENT, Fabrice ,  LANDRU, Didier ,  LANDRY, Karine ,  SHAHEEN, Mohamad ,  MAZURE, Carlos

IPC分类号： H01L29/78

CPC分类号： H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10
10 charges/cm
2 . The invention also relates to a process for making such a substrate.

公开(公告)号：EP2016205A2

公开(公告)日：2009-01-21

申请号：EP07775131.1

申请日：2007-04-09

申请人： S.O.I.TEC Silicon on Insulator Technologies S.A.

发明人： CODY, Nyles, W. ,  ARENA, Chantel ,  TOMASINI, Pierre ,  MAZURE, Carlos

IPC分类号： C23C16/22 ,  C23C16/24 ,  C23C16/455 ,  C30B25/02 ,  C30B29/02 ,  C30B25/14 ,  C30B29/06

CPC分类号： C23C16/22 ,  C23C16/24 ,  C23C16/45523 ,  C30B25/165 ,  C30B29/52

摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.

摘要翻译： 通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。 在形成渐变的SiGe缓冲层期间，从硅前体和锗前体的SiGe的沉积被中断一次或多次，其中停止向硅衬底的硅前驱体的流动，同时锗前体流向 保持底物。

公开(公告)号：EP1423873B1

公开(公告)日：2006-03-08

申请号：EP02794814.0

申请日：2002-08-14

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： RAYSSAC, Olivier ,  MAZURE, Carlos ,  GHYSELEN, Bruno

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The invention concerns a method for obtaining a self-supported thin film made of a semiconductor material, supporting at least an electronic component and/or circuit (3) one of its surfaces, from a wafer (1) of said material, the latter including a front side (2), supporting or designed to support at least an electronic component and/or circuit (3) and a rear side (4'). Said method is characterised in that it comprises steps which consist in: a) implanting atomic species inside said wafer (1), from its rear side (4, 4'), so as to obtain a weakened zone (5) delimiting a front part (6) extending from said front side (2) to said weakened zone (5) and a rear part (7) formed by the rest of the wafer (1); d) removing said rear part (7), the front part (6); repeating, if required, steps a) and b) on the rear side of said front part (6) until the latter has the desired thickness for forming said self-supported thin film.