公开(公告)号：EP1447851A4

公开(公告)日：2008-10-29

申请号：EP02788619

申请日：2002-11-18

申请人： SHARP KK

发明人： IWATA HIROSHI ,  SHIBATA AKIHIDE

IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L27/22 ,  H01L29/423 ,  H01L29/792

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/118 ,  H01L27/1203 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

摘要翻译： 本发明提供具有半导体存储装置：在半导体层中形成的第一导电类型区; 在与所述第一导电类型区相接触的半导体层中形成的第二导电类型区; 横跨所述第一和第二导电类型区的边界的半导体层上的存储功能元件; 并与所述存储功能元件接触，并通过在绝缘片上的第一导电型区域的电极提供，以及便携式电子设备，包括半导体存储装置。 本发明可以充分通过基本上构成一个装置的可选择的存储单元与按比例缩小和高集成应付。

公开(公告)号：EP1335425A4

公开(公告)日：2008-10-08

申请号：EP01976761

申请日：2001-10-19

申请人： SHARP KK

发明人： IWATA HIROSHI ,  SHIBATA AKIHIDE ,  KAKIMOTO SEIZO

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823481 ,  H01L21/761 ,  H01L21/76202 ,  H01L21/76232 ,  H01L21/823493

摘要： A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a variable substrate-bias transistor and a DTMOS. Field-effect transistors (223) are fabricated on a P-type shallow well region (212). The depth of a shallow element-isolating region (214) over the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field-effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep element-isolating region (226) and the N-type deep well region (227).

公开(公告)号：EP1246258A4

公开(公告)日：2007-07-18

申请号：EP00986014

申请日：2000-12-28

申请人： SHARP KK

发明人： IWATA HIROSHI ,  SHIBATA AKIHIDE ,  KAKIMOTO SEIZO ,  ADACHI KOUICHIRO ,  NAKANO MASAYUKI

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device (1910) comprises a semiconductor substrate (100) including an isolation region (101) and an active region (102); a gate electrode (104) formed on gate oxide film (103) over the active area (102) and including side walls covered at least in part by insulating film (105) of the gate electrode side wall; and a source region (106) and a drain region (106) provided across the gate electrode (104) with the insulating film (105) of the gate electrode side wall in between. At least any of the source region (106) and the drain region (106) includes a second face for engagement with contact wiring. The second face makes some angle with the first face (AA') and an angle of less than 80 degrees with the surface of the isolation region.

公开(公告)号：EP2546900A4

公开(公告)日：2016-02-17

申请号：EP11753178

申请日：2011-02-22

申请人： SHARP KK

发明人： NEGISHI TETSU ,  SHIBATA AKIHIDE ,  KOMIYA KENJI ,  YOSHIOKA FUMIYOSHI ,  IWATA HIROSHI ,  TAKAHASHI AKIRA

IPC分类号： H01L33/62 ,  G02F1/1335 ,  G02F1/13357 ,  H01L33/20

CPC分类号： G02F1/133603 ,  F21K9/00 ,  G02F1/133605 ,  G02F2001/133612 ,  G02F2001/133614 ,  G02F2001/133628 ,  H01L24/95 ,  H01L25/0753 ,  H01L33/06 ,  H01L33/18 ,  H01L33/20 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/09701 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2933/0041 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

公开(公告)号：EP1343207A4

公开(公告)日：2008-01-23

申请号：EP01982765

申请日：2001-11-13

申请人： SHARP KK

发明人： SHIBATA AKIHIDE ,  IWATA HIROSHI ,  KAKIMOTO SEIZO

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  G06F17/60 ,  H01L27/085

CPC分类号： H01L21/76229 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0921

摘要： A semiconductor device of low power consumption and high reliability with a DTMOS and a substrate bias variable transistor and a portable electronic apparatus comprising this semiconductor device. This device has three layer well regions (12, 14, 16; 13, 15, 16) on a semiconductor substrate (11) and is provided with DTMOSs (29, 30), and substrate bias variable transistors (27, 28) in shallow well regions (16, 17). A boundary which constitutes a PNP, an NPN, or an NPNP structure is provided with wide element isolating regions (181, 182, 183), but a narrow element isolating region (18) when both the well regions have the same conductivity type. Thus, a plurality of well regions of respective conductivity types provided with substrate bias variable transistors (27, 28) of the respective conductivity types are made electrically independent to reduce power consumption and to suppress latchup phenomenon.

公开(公告)号：EP1357598A4

公开(公告)日：2007-10-10

申请号：EP01271852

申请日：2001-12-21

申请人： SHARP KK

发明人： SHIBATA AKIHIDE ,  IWATA HIROSHI ,  KAKIMOTO SEIZO

IPC分类号： H01L21/822 ,  H01L21/761 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L27/08 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

摘要： A semiconductor device comprising a DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions (12) are formed in one P-type semiconductor substrate (11). The N-type deep well regions (12, 12) are electrically isolated by the P-type semiconductor substrate (11). Over the N-type deep well regions (12), a P-type deep well region (13) and a P-type shallow well region (15) are formed to fabricate an N-type substrate variable-bias transistor (26). Over the N-type deep well region (12), an N-type shallow well region (14) is formed to fabricate a P-type substrate variable-bias transistor (25). Further a P-type DTMOS (28) and an N-type DTMOD (27) are fabricated.