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    Method of connecting a dram trench capacitor
    2.
    发明公开
    Method of connecting a dram trench capacitor 失效
    KontaktierverfahrenfürDRAM-Grabenkondensator

    公开(公告)号：EP0791959A1

    公开(公告)日：1997-08-27

    申请号：EP97102361.9

    申请日：1997-02-13

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Stengl, Reinhard J. ,  Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Srinivasan, Radhika ,  Short, Alvin P.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

    摘要翻译： 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，电连接（90）通过有选择地控制在沟槽中存在的N型或P型掺杂剂的扩散扩散形成 通过从沟槽侧壁外延（epi）生长的单晶半导体材料（60）。 这种外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

    DRAM trench capacitor with insulating collar
    3.
    发明公开
    DRAM trench capacitor with insulating collar 失效
    DRAM严重电容器绝缘环

    公开(公告)号：EP0794576A3

    公开(公告)日：2004-01-07

    申请号：EP97102980.6

    申请日：1997-02-24

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Hammerl, Erwin ,  Ho, Herbert L.

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/94

    CPC分类号： H01L27/10861

    摘要： A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench (33) into the oxide collar which surrounds the polysilicon trench fill (35) and isolating it from the single crystal semiconducting substrate material (30) of the DRAM cell to a depth which is at least equal to or larger than the width of the oxide collar. A nitride layer (40) with a thickness equal to or thicker than half of the width of the oxide collar is then deposited on the top surface of the freshly excavated oxide collar such that the aforementioned trench is completely filled with this nitride layer, and the entire surfaces of the substrate and polysilicon trench fill are completely covered. The newly formed nitride layer is then selectively overetched in order to completely remove it from the substrate and polysilicon trench fill surfaces, while still maintaining a sufficient thickness of this layer disposed on the oxide collar sufficient to prevent oxygen diffusion into the oxide collar. Alternatively, the nitride layer may be deposited as a thin layer sandwiched between the original oxide collar and an additional thermally deposited oxide layer.

    DRAM cell with trench capacitor
    4.
    发明公开
    DRAM cell with trench capacitor 审中-公开
    DRAM-Zelle mit Grabenkondensator

    公开(公告)号：EP0901168A3

    公开(公告)日：2001-10-10

    申请号：EP98307178.8

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Short, Alvin P. ,  Stengl, Reinhard J. ,  Ho, Herbert L. ,  Poschenrieder, Bernhard ,  Srinivasan, Radhika

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10873

    摘要： A method for forming a trench capacitator dynamic random access memory comprising the steps of: providing a substrate (305) having a single crystalline structure and a substantially planar substrate surface, wherein the substrate surface comprises a pad layer having a substantially planar pad surface; fabricating a trench capacitor (315) in the substrate, wherein the trench capacitor comprises polysilicon; recessing the poly in the trench capacitor below the surface of the substrate to form a depression; forming an intermediate layer in the depression to a height above the pad surface, the intermediate layer having a single crystalline top plane (260); planarizing the intermediate layer and the pad surface such that the top plane of the intermediate layer is substantially planar with the substrate surface; and fabricating a transistor (370) on the top plane, wherein the active region of the second device is within the top plane.

    摘要翻译： 公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。 在第一装置的上方形成具有单晶顶表面的层，以提供用于形成第二装置的有效区域的基座。

    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed
    5.
    发明公开
    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed 失效
    一种用于生产通过受控再结晶在由此制造的半导体存储器件和半导体存储器件的掩埋连接处理

    公开(公告)号：EP0739033A3

    公开(公告)日：2000-01-12

    申请号：EP96105064.8

    申请日：1996-03-29

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT ,  KABUSHIKI KAISHA TOSHIBA

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Shiozawa, Junichi ,  Stengl, Reinhard Johannes

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/74 ,  H01L21/225

    CPC分类号： H01L27/10861

    摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate (10) and an impurity-doped first conductive region (105) is then formed by filing the trench with an impurity-doped first conductive material. The impurity-doped first conductive region (105) is etched back to a first level within the trench. An insulating layer (106) is then formed on a sidewall of the portion of the trench (103) opened by the etching back of the impurity-doped first conductive region and a second conductive region (107) is formed by filing the remainder of the trench with a second conductive material. The insulating layer (106) and the second conductive region (107) are etched back to a second level within the trench and an amorphous silicon layer (108) is formed in the portion of the trench opened by the etching back of the insulating layer (106) and the second conductive region (107). The undoped amorphous silicon layer (108) is etched back to a third level within the trench. The undoped amorphous silicon layer (108) is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap (126) for electrically connecting the first and second conductive layers in the trench to the source/drain region.

    Process for forming a deep trench-type storage node for a DRAM
    6.
    发明公开
    Process for forming a deep trench-type storage node for a DRAM 失效
    Verfahren zur Herstellung eines Speicherknotens mit TiefgrabenstrukturfürDRAM

    公开(公告)号：EP0794567A2

    公开(公告)日：1997-09-10

    申请号：EP97102901.2

    申请日：1997-02-21

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ho, Herbert L. ,  Srinivasan, Radhika ,  Halle, Scott D. ,  Hammerl, Erwin ,  Dobuzinsky, David M. ,  Mandelman, Jack A. ,  Jaso, Mark Anthony

    IPC分类号： H01L21/70 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

    摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

    摘要翻译： 在半导体衬底上制造用于深沟槽型DRAM的存储节点包括蚀刻衬底中的沟槽，在侧壁上形成电介质层，并部分地去除其以暴露侧壁的上部的下部区域，在其上具有层 的氧化物生长。 然后去除部分氧化物以使该层从基板表面定向给定距离，然后用半导体填充沟槽。 还要求保护的是另一种方法，其中节点电介质（20）沉积在侧壁上，生长氧化物环（24），填充有抗蚀剂的沟槽被蚀刻以去除上述的氧化物环的一部分，并且沟槽 充满多晶硅（30）。

    DRAM trench capacitor and method of fabricating the same
    7.
    发明公开
    DRAM trench capacitor and method of fabricating the same 审中-公开
    Graben-KondensatorfürDRAM und Verfahren zur Herstellung desselben

    公开(公告)号：EP0962972A1

    公开(公告)日：1999-12-08

    申请号：EP99304168.0

    申请日：1999-05-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Economikos, Laertis ,  Gruening, Ulrike ,  Ho, Herbert L. ,  Radens, Carl J. ,  Jammy, Ragarao ,  Hoepfner, Joachim ,  Shen, Hua

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sidewall, growing a layer of oxide (16) on the upper portion of the sidewall, removing the remainder of the layer of dielectric material, doping to form a buried plate (17), forming a node dielectric (18), and forming an inner electrode (19) within the trench. The oxide layer at the upper portion of the trench is preferably formed by a LOCOS technique.

    摘要翻译： 通过在半导体衬底（10）的表面上蚀刻沟槽（11）形成用于深沟槽存储电容器的存储节点，在沟槽的侧壁上形成电介质层（14），部分地去除 电介质材料以暴露侧壁的上部，在侧壁的上部生长一层氧化物（16），去除电介质材料层的其余部分，掺杂以形成掩埋板（17），形成 节点电介质（18），并且在所述沟槽内形成内部电极（19）。 沟槽上部的氧化物层优选通过LOCOS技术形成。

    DRAM trench capacitor with insulating collar
    8.
    发明公开
    DRAM trench capacitor with insulating collar 失效
    DRAM-Grabenkondensator mit isolierendem Ring

    公开(公告)号：EP0794576A2

    公开(公告)日：1997-09-10

    申请号：EP97102980.6

    申请日：1997-02-24

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Hammerl, Erwin ,  Ho, Herbert L.

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10861

    摘要： A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench into the oxide collar which surrounds the polysilicon trench fill and isolating it from the single crystal semiconducting substrate material of the DRAM cell to a depth which is at least equal to or larger than the width of the oxide collar. A nitride layer with a thickness equal to or thicker than half of the width of the oxide collar is then deposited on the top surface of the freshly excavated oxide collar such that the aforementioned trench is completely filled with this nitride layer, and the entire surfaces of the substrate and polysilicon trench fill are completely covered. The newly formed nitride layer is then selectively overetched in order to completely remove it from the substrate and polysilicon trench fill surfaces, while still maintaining a sufficient thickness of this layer disposed on the oxide collar sufficient to prevent oxygen diffusion into the oxide collar. Alternatively, the nitride layer may be deposited as a thin layer sandwiched between the original oxide collar and an additional thermally deposited oxide layer.

    摘要翻译： 一种用于在DRAM单元中的沟槽电容器的氧化物环上形成不透氧屏障的方法。 该过程包括将浅沟槽（33）蚀刻到围绕多晶硅沟槽填充物（35）的氧化物环中并将其与DRAM单元的单晶半导体衬底材料（30）隔离至至少等于 或大于氧化物套环的宽度。 然后将厚度等于或大于氧化物环的宽度的一半的氮化物层（40）沉积在新挖出的氧化物环的顶表面上，使得上述沟槽被该氮化物层完全填充，并且 衬底和多晶硅沟槽填充的整个表面被完全覆盖。 然后，新形成的氮化物层被选择性地过蚀刻，以便将其从衬底和多晶硅沟槽填充表面完全去除，同时仍保持设置在氧化物环上的该层的足够厚度足以防止氧气扩散进入氧化物套环。 或者，可以将氮化物层沉积成夹在原始氧化物环和另外的热沉积氧化物层之间的薄层。

    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed
    9.
    发明公开
    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed 失效
    一种用于生产通过受控再结晶在由此制造的半导体存储器件和半导体存储器件的掩埋连接处理

    公开(公告)号：EP0739033A2

    公开(公告)日：1996-10-23

    申请号：EP96105064.8

    申请日：1996-03-29

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT ,  KABUSHIKI KAISHA TOSHIBA

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Shiozawa, Junichi ,  Stengl, Reinhard Johannes

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/74 ,  H01L21/225

    CPC分类号： H01L27/10861

    摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate (10) and an impurity-doped first conductive region (105) is then formed by filing the trench with an impurity-doped first conductive material. The impurity-doped first conductive region (105) is etched back to a first level within the trench. An insulating layer (106) is then formed on a sidewall of the portion of the trench (103) opened by the etching back of the impurity-doped first conductive region and a second conductive region (107) is formed by filing the remainder of the trench with a second conductive material. The insulating layer (106) and the second conductive region (107) are etched back to a second level within the trench and an amorphous silicon layer (108) is formed in the portion of the trench opened by the etching back of the insulating layer (106) and the second conductive region (107). The undoped amorphous silicon layer (108) is etched back to a third level within the trench. The undoped amorphous silicon layer (108) is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap (126) for electrically connecting the first and second conductive layers in the trench to the source/drain region.

    摘要翻译： 形成耦合电容器和晶体管包括：（a）形成在半导体衬底的沟槽; （B）通过填充在掺杂有杂质的第一导电材料的沟槽中形成掺杂有杂质的第一导电区域的; （C）回蚀刻掺杂有杂质的第一导电区域，以在所述沟槽内的第一电平; （D）上形成由所述回蚀刻开设沟槽的部分的侧壁绝缘层; （E）通过填充有第二导电材料的沟槽的剩余部分形成第二导电区域; （F）回蚀刻绝缘层和第二导电材料，以在所述沟槽内的第二电平; （G）在由所述绝缘层和所述第二导电区域的蚀刻开设背面沟槽的部分未掺杂非晶硅层的形成; （H）回蚀刻未掺杂的无定形硅层，以在沟槽内的第三电平; （I）重结晶所述非晶硅层; （J）扩散出从杂质掺杂第一导电区域通过重结晶Si层的半导体衬底的杂质; （K）形成源极/在所述沟槽和所述底物的表面的交叉点漏毗邻晶体管的区域中，扩散出来的杂质和构成隐埋条用于电重结晶Si层连接在所述第一和第二导电层 沟槽到源极/漏极区域。