公开(公告)号：EP2052407B1

公开(公告)日：2015-07-01

申请号：EP07797046.5

申请日：2007-07-27

申请人： SanDisk Corporation

发明人： NALLABOLU, Madhuri, L. ,  LIU, Chao ,  DUAN, Xiangfeng ,  CHEN, Jian ,  PARCE, J., Wallace ,  CRUDEN, Karen, Chu ,  RANGANATHAN, Srikanth

IPC分类号： H01L21/28 ,  H01L21/3105 ,  G03F7/075 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00

CPC分类号： H01L21/28008 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/28229 ,  H01L21/28273 ,  H01L21/3105 ,  Y10S977/774 ,  Y10S977/782 ,  Y10S977/845 ,  Y10S977/855 ,  Y10S977/89 ,  Y10S977/891

公开(公告)号：EP1324343B1

公开(公告)日：2014-05-07

申请号：EP02001104.5

申请日：2002-01-23

申请人： Kabushiki Kaisha Toshiba ,  SanDisk Corporation

发明人： Tanaka, Tomoharu ,  Chen, Jian

IPC分类号： G11C11/56

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell (M), and a write circuit (2 to 8) for writing data in the memory cell, the write circuit writing a data in the memory cells, the writing a data in the memory cell by supplying a write voltage (Vpgm) and a write control voltage (VBL) to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage (VBL) in response to the advent of a first write state of the memory cell, and inhibiting any operation of writing a data to the memory cell (M) by further changing the value of the write control voltage (VBL) to Vdd in response to the advent of a second write state of the memory cell.

公开(公告)号：EP1814122B1

公开(公告)日：2013-05-15

申请号：EP07006344.1

申请日：2002-06-26

申请人： SanDisk Corporation ,  Kabushiki Kaisha Toshiba

发明人： Chen, Jian ,  Fong, Yupin ,  Tanaka, Tomoharu ,  Quader, Khandker N.

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/12

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

公开(公告)号：EP2312449B1

公开(公告)日：2013-04-24

申请号：EP10075594.1

申请日：2001-08-14

申请人： Sandisk Corporation

发明人： Cedar, Yoram ,  Holtzman, Micky ,  Pinto, Yosi

IPC分类号： G06F13/38 ,  G06F12/06

CPC分类号： G06F13/1694 ,  G06F12/0653 ,  G06F12/0661 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2213/0052

公开(公告)号：EP1975942B1

公开(公告)日：2012-06-06

申请号：EP07076027.7

申请日：2003-12-18

申请人： SanDisk Corporation ,  Kabushiki Kaisha Toshiba

发明人： Chen, Jian ,  Tanaka, Tomoharu, c/o Intellectual Property Div.

IPC分类号： G11C16/34

CPC分类号： G11C11/5635 ,  G06F11/1068 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5646

公开(公告)号：EP2434426A1

公开(公告)日：2012-03-28

申请号：EP11194701.6

申请日：2008-03-26

申请人： SanDisk Corporation

发明人： Jogand-Coulomb, Fabrice

IPC分类号： G06F21/00 ,  G11B20/00

CPC分类号： G11B20/00818 ,  G06F21/10 ,  G11B20/00086 ,  G11B20/0021 ,  G11B20/00833 ,  G11B20/00847 ,  G11B20/10527 ,  G11B2020/10546 ,  G11B2020/10703 ,  G11B2020/10759

摘要： A storage system is provided that includes a memory controller for controlling a throughput rate for utilizing digital content by an accessing system, wherein the throughput rate is associated with information related to the digital content stored as a file. Also, a system for utilizing digital content is provided. The system includes an accessing system for utilizing the digital content, wherein the digital content is released to the accessing system at a controlled throughput rate and the throughput rate is associated with information related to the digital content stored as a file.

摘要翻译： 提供了一种存储系统，其包括存储器控制器，用于控制由访问系统利用数字内容的吞吐率，其中吞吐率与与作为文件存储的数字内容相关的信息相关联。 另外，提供了一种利用数字内容的系统。 该系统包括用于利用数字内容的访问系统，其中数字内容以受控的吞吐率被释放到访问系统，并且吞吐率与与作为文件存储的数字内容相关的信息相关联。

公开(公告)号：EP1828948B1

公开(公告)日：2012-02-08

申请号：EP05855187.0

申请日：2005-12-21

申请人： SanDisk Corporation ,  Discretix Technologies Ltd.

发明人： HOLTZMAN, Michael ,  COHEN, Baruch Boris ,  DEITCHER, David ,  BAR-EL, Hagai ,  YERUCHAMI, Aviram

IPC分类号： G06F21/00

CPC分类号： G06F21/78

摘要： The throughput of the memory system is improved where data in a data stream is cryptographically processed by a circuit without involving intimately any controller. The data stream is preferably controlled so that it has a selected data source among a plurality of sources and a selected destination among a plurality of destinations, all without involving the controller. The cryptographic circuit may preferably be configured to enable the processing of multiple pages, selection of one or more cryptographic algorithms among a plurality of algorithms to encryption and/or decryption without involving a controller, and to process data cryptographically in multiple successive stages without involvement of the controller. For a memory system cryptographically processing data from multiple data streams in an interleaved manner, when a session is interrupted, security configuration information may be lost so that it may become impossible to continue the process when the session is resumed. To retain the security configuration information, the controller preferably causes the security configuration information for the session to be stored before the interruption so that it is retrievable after the interruption.

公开(公告)号：EP2301033B1

公开(公告)日：2011-11-30

申请号：EP09770884.6

申请日：2009-06-23

申请人： Sandisk Corporation

发明人： LEE, Dana ,  DUTTA, Deepanshu ,  DONG, Yingda

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.

摘要翻译： 在多程序编程过程中，编程时间在非易失性存储器中减少。 在第一次编程过程中，高状态单元通过一系列编程脉冲来编程，以识别快速和慢速高状态单元，而较低状态单元被锁定编程。 一旦识别，快速高状态单元暂时被锁定编程，而慢速高状态单元继续被编程为其最终预期状态。 此外，编程脉冲急剧增加以编程慢速高状态单元。 在第二遍编程中，快速高状态单元与其他较低状态单元一起编程，直到它们全部达到它们各自的预期状态。 与其中所有高状态单元在第一遍编程中被编程的方法相比，节省了时间。

公开(公告)号：EP2015310B1

公开(公告)日：2011-11-09

申请号：EP08004345.8

申请日：2004-09-16

申请人： SanDisk Corporation ,  Kabushiki Kaisha Toshiba

发明人： Lutze, Jeffrey ,  Chen, Jian ,  Li, Yan ,  Kanebako, Kazunori ,  Tanaka, Tomoharu

IPC分类号： G11C16/34 ,  G11C29/00

CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

公开(公告)号：EP2016590B1

公开(公告)日：2011-10-26

申请号：EP07783139.4

申请日：2007-05-02

申请人： SanDisk Corporation

发明人： LI, Yan

IPC分类号： G11C16/26 ,  G11C11/56 ,  G11C7/22

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2207/107 ,  G11C2207/2245 ,  G11C2207/2281

摘要： Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A scheme for caching read data is implemented so that even when the read for a current page on a current wordline must be preceded by a prerequisite read of data on an adjacent wordline, the prerequisite read along with any I/O access is preemptively done in the cycle for reading a previous page so that the current read can be performed while the previously read page is busy with the I/O access.