公开(公告)号：EP2056117A1

公开(公告)日：2009-05-06

申请号：EP07119668.7

申请日：2007-10-30

申请人： ISMECA Semiconductor Holding SA

发明人： Charpié, Michel ,  Cretenet, Davy

IPC分类号： G01R31/12 ,  G01R31/26 ,  G01R31/28 ,  G01R31/02

CPC分类号： G01R31/129 ,  G01R31/025 ,  G01R31/263 ,  G01R31/2642 ,  G01R31/2851 ,  G01R31/2896

摘要： A test station (6) for testing leakage current through the insulating package (42) of power electronic components (3), said test station comprising:
first contact portions (36) for applying a first test voltage on one or more pins (40) of said tested components,
second contact portions (24, 37, 370, 25, 26) for applying a second test voltage on several external faces of said insulating package of said tested components,

characterized in that said second contact portions are arranged for contacting several mutually orthogonal faces of said power electronic components (3).

摘要翻译： 的测试站（6），用于检测泄漏电流通过功率电子器件的绝缘封装（42）（3）所述测试站包括：用于在一个或多个销施加第一测试电压的第一接触部（36）（40） 的所述测试器件，第二接触部分（24，37，370，25，26），用于在所述的若干外表面施加第二测试电压施加到所述的绝缘封装测试的组件，在其特点，所述第二接触部分布置成用于接触几 所述功率电子部件的相互正交的面（3）。

公开(公告)号：EP2965348B1

公开(公告)日：2017-12-20

申请号：EP14713702.0

申请日：2014-03-06

申请人： Xilinx, Inc.

发明人： LOWNEY, Donnacha ,  DE LA TORRE, Marites

IPC分类号： H01L21/66 ,  H01L25/065 ,  G01R31/3187 ,  G01R31/28 ,  H01L23/498 ,  H01L23/58 ,  G01R31/3185

CPC分类号： G01R31/2896 ,  G01R31/31855 ,  H01L22/34 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/58 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

公开(公告)号：EP3104277B1

公开(公告)日：2017-11-22

申请号：EP16172421.6

申请日：2016-06-01

申请人： Altera Corporation

发明人： How, Dana ,  Patil, Dinesh ,  Rahman, Arifur ,  Schulz, Jeffrey Erik

IPC分类号： G06F11/16 ,  G06F11/18 ,  G06F11/20

CPC分类号： G01R31/318597 ,  G01R31/2896 ,  G06F11/00 ,  G06F11/1625 ,  G06F11/186 ,  G06F11/2007 ,  H01L25/0652 ,  H01L2225/06527

摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

公开(公告)号：EP2965348A1

公开(公告)日：2016-01-13

申请号：EP14713702.0

申请日：2014-03-06

申请人： Xilinx, Inc.

发明人： LOWNEY, Donnacha ,  DE LA TORRE, Marites

IPC分类号： H01L21/66 ,  H01L25/065 ,  G01R31/3187 ,  G01R31/3185

CPC分类号： G01R31/2896 ,  G01R31/31855 ,  H01L22/34 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/58 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

摘要： An apparatus with package integrity monitoring capability, includes: a package (100) having a die (102) connected to an interposer (104) through a plurality of bumps (106, 108), wherein at least some of the bumps comprise dummy bumps (106); a package integrity monitor (202) having a transmitter (204) to transmit a test signal and a receiver (206) to receive the test signal; and a first scan chain (208) comprising a plurality of alternating interconnects (210, 212) in the die (102) and in the interposer (104) connecting some of the dummy bumps (106) in series, wherein the first scan chain (208) has a first end coupled to the transmitter (204) of the package integrity monitor (202) and a second end coupled to the receiver (206) of the package integrity monitor (202).

摘要翻译： 一种具有封装完整性监测功能的装置，包括：具有通过多个凸块连接到插入件的管芯的封装，其中至少一些凸块包括虚拟凸块; 封装完整性监视器，具有发送测试信号的发送器和接收器以接收测试信号; 以及第一扫描链，其包括在所述管芯中的所述多个交替互连件和所述插入器中，所述插入器将一些所述虚设凸起串联连接，其中所述第一扫描链具有耦合到所述封装完整性监视器的所述发射器的第一端， 到包装完整性监视器的接收器。

公开(公告)号：EP2817824A1

公开(公告)日：2014-12-31

申请号：EP12869035.1

申请日：2012-02-24

申请人： Freescale Semiconductor, Inc.

发明人： BODE, Hubert

IPC分类号： H01L23/52

CPC分类号： G01R31/2896 ,  G01R31/2853 ,  G05F1/462 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device for use in a package comprising an output pin (310) and a reference pin (320) is described. The semiconductor device comprises a plurality of output pads (1 1 1, 1 12) bondable to the output pin (310), a plurality of reference pads (121, 122) bondable to the reference pin (320), and an output driver circuitry (400). The output driver circuitry (400) has a control terminal (400C) for receiving a control signal and arranged to drive the plurality of output pads (111, 112) relative to the plurality of reference pads (121, 122) in dependence on the control signal. The output driver circuitry comprises a plurality of driver sections (401, 402) and a selection circuitry (600). Each driver section is arranged to drive an output pad (111; 112) relative to the single reference pad (121; 122) in dependence on a respective section control signal. The plurality of reference pads (121, 122) is connected in a one-to-one relationship to the plurality of driver sections (401, 402). The plurality of output pads (111, 112) is connected in a one-to-one relationship to the plurality of driver sections (401, 402). The selection circuitry is arranged to provide the respective section control signals to the plurality of driver sections (401, 402) in dependence on at least one selection signal and the control signal. A packaged semiconductor device, a method of testing and a method of conditioning are also described.

公开(公告)号：EP1946085A1

公开(公告)日：2008-07-23

申请号：EP06816634.7

申请日：2006-10-11

申请人： Delta Design, Inc.

发明人： DING, Kexiang, Ken

IPC分类号： G01N21/956 ,  H01L21/66

CPC分类号： G01N21/95684 ,  G01N2021/8822 ,  G01R31/046 ,  G01R31/2896

摘要： An inspection system (1), for inspecting pin grid arrays (15) on integrated circuit devices (10) includes a pin base mask (30) configured to receive a device having a pin grid array (15) . A dark-field, low-angle lighting system (40) emits light onto the pin grid array (15) . The pin base mask (30) and low-angle lighting system (40) provide for a clear and definitive image of the pin grid array (15) . A camera (50) captures the image of the pin grid array (15). A processor (90) , coupled to the camera (50) , analyzes the images captured by the camera (50) . Based on the captured image, the processor (90) determines whether any pins on the pin grid array (15) are bent (13, 14) or missing, or whether there are extra pins present.

公开(公告)号：EP3372995A1

公开(公告)日：2018-09-12

申请号：EP18275035.6

申请日：2018-03-06

申请人： Carbice Corporation

发明人： Cola, Baratunde ,  Prinzi, Leonardo ,  Green, Craig

IPC分类号： G01N25/18 ,  B82Y30/00 ,  C09K5/14 ,  C01B32/15

CPC分类号： H01L23/3735 ,  B82Y30/00 ,  B82Y40/00 ,  C01B2202/24 ,  C09K5/14 ,  G01N25/18 ,  G01R31/2896 ,  H01L23/3731 ,  H01L24/48 ,  H05K7/20481 ,  H05K2201/026 ,  H05K2201/10151

摘要： A method for testing thermal interface materials (TIMs) that comprise stacks of vertically aligned carbon nanotube (CNT) arrays, wherein the thermal interface material is provided as an adhesive foil substrate and is compressed between a heat-generating electronic device and a heat sink and exposed to at least 1500 thermal cycles.

公开(公告)号：EP3066485A1

公开(公告)日：2016-09-14

申请号：EP14799072.5

申请日：2014-10-28

申请人： Qualcomm Incorporated

发明人： BHOGELA, Sagar ,  CYNTHIA, Daisy ,  SRINIVASAN, Srikanth

IPC分类号： G01R31/3185

CPC分类号： G01R31/2896 ,  G01R31/2894 ,  G01R31/318513 ,  G01R31/318558

摘要： An integrated circuit is disclosed. The integrated circuit includes input and output pads, a first integrated circuit portion having first circuitry, and a second integrated circuit portion having second circuitry different from the first circuitry. The first integrated circuit portion is configured to provide an input test signal from the input pad to the second integrated circuit portion, and provide an output test signal from the second integrated circuit portion to the output pad, the output test signal being generated by second integrated circuit portion in response to the input test signal.

公开(公告)号：EP2851697A1

公开(公告)日：2015-03-25

申请号：EP14185018.0

申请日：2014-09-16

申请人： TOKYO ELECTRON LIMITED

发明人： Murata, Michio ,  Morita, Shingo ,  Narikawa, Kenichi

IPC分类号： G01R31/28

CPC分类号： G01R31/2889 ,  G01R31/2846 ,  G01R31/2896

摘要： A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.

摘要翻译： 基板检查装置能够有效地检查半导体装置的电气特性。 探测器10包括具有多个探针17的探针卡15，以便与形成在晶片W上的半导体器件的电极接触; 以及电连接到探针卡15的测试盒14.探针卡15的卡侧检查电路在与晶片W分离之后再现要安装半导体器件的电路配置，例如， 功能扩展卡和测试箱14的盒侧检查电路21再现要安装半导体器件的电路配置，例如母板的电路配置的一部分。

公开(公告)号：EP1792871A2

公开(公告)日：2007-06-06

申请号：EP06077085.6

申请日：2006-11-23

申请人： Delphi Technologies, Inc.

发明人： Dewes, Brian E. ,  Dewes, Denise R. ,  Harlan, Richard D.

IPC分类号： B81C5/00

CPC分类号： G01M3/40 ,  B81C99/0045 ,  G01R31/2896 ,  H01L22/12

摘要： A method and structure use characteristics of a plasma discharge for verifying a hermetic seal. The plasma discharge is created in a hermetically sealed cavity by a pair of spaced electrodes that extend from tips inside the hermetically sealed cavity to contacts outside the sealed cavity. An electrical bias is applied to the contacts that is sufficient to create a plasma discharge in a properly hermetically sealed cavity but not in an unsealed cavity.

摘要翻译： 用于验证气密密封的等离子体放电的方法和结构使用特性。 等离子体放电通过一对间隔开的电极在气密密封的腔中产生，该电极从气密密封腔内的尖端延伸以接触密封空腔外部。 电气偏压被施加到触点上，足以在适当的气密密封腔中产生等离子体放电，但不在未密封腔中。