公开(公告)号：EP1791253B1

公开(公告)日：2017-12-13

申请号：EP06023734.4

申请日：2006-11-15

Applicant: NTT DOCOMO, INC.

Inventor： Fukuda, Atsushi NTT DOCOMO, INC. ,  Okazaki, Hiroshi NTT DOCOMO, INC. ,  Narahashi, Shoichi NTT DOCOMO, INC.

IPC: H03F1/08 ,  H03F3/191 ,  H03F3/60 ,  H03F1/56 ,  H03H7/40 ,  H03H11/30 ,  H04B1/04 ,  H04B1/00

CPC classification number: H03F3/601 ,  H03F1/086 ,  H03F1/56 ,  H03F3/191 ,  H03F2200/111 ,  H03F2200/12 ,  H03F2200/222 ,  H03F2200/249 ,  H03F2200/252 ,  H03F2200/255 ,  H03F2200/27 ,  H03F2200/372 ,  H03F2200/387 ,  H03F2200/417 ,  H03F2200/423 ,  H03H7/40 ,  H03H11/30 ,  H04B1/0053 ,  H04B1/0458

Abstract: A stabilization circuit (100) which comprises: serial stabilization blocks (110,120) connected in series, with respect to a signal to be amplified, with an amplification element; parallel stabilization blocks (130,140) connected in parallel with the amplification element, with respect to a signal to be amplified; and a switch part (150) capable of connecting and disconnecting said parallel stabilization block (140), with respect to a signal to be amplified.

公开(公告)号：EP2262106B1

公开(公告)日：2016-08-10

申请号：EP09251545.1

申请日：2009-06-12

Applicant: ST-Ericsson SA

Inventor： Putter, Bas

IPC: H03F3/00 ,  H03F3/187 ,  H03H19/00

CPC classification number: H03F3/005 ,  H03F3/187 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2200/417 ,  H03H19/004

公开(公告)号：EP2372906B1

公开(公告)日：2016-01-06

申请号：EP11250063.2

申请日：2011-01-20

Applicant: Sony Europe Limited

Inventor： Clifton, John Christopher

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/24 ,  H03F3/72 ,  H03F3/21

CPC classification number: H03F1/0222 ,  H03F1/0261 ,  H03F1/0277 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/171 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/271 ,  H03F2200/366 ,  H03F2200/405 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2200/471 ,  H03F2200/504 ,  H03F2200/507 ,  H03F2200/511 ,  H03F2200/516 ,  H03F2200/525 ,  H03F2200/54 ,  H03F2203/21145 ,  H03F2203/21157 ,  H03F2203/21175 ,  H03F2203/21178 ,  H03F2203/21193 ,  H03F2203/7206 ,  H03F2203/7209 ,  H03F2203/7227 ,  H03F2203/7236

公开(公告)号：EP2834916A1

公开(公告)日：2015-02-11

申请号：EP13714313.7

申请日：2013-04-05

Applicant: ST-Ericsson SA

Inventor： DIETER, Joos ,  PHILIBERT, Wim ,  REYNAERT, Patrick ,  ZHAO, Dixian

IPC: H03F3/195 ,  H03H7/48 ,  H03F1/02

CPC classification number: H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/72 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/222 ,  H03F2200/312 ,  H03F2200/396 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/72 ,  H03F2200/75 ,  H03F2203/21106 ,  H03F2203/21142 ,  H03F2203/21175 ,  H03F2203/45018 ,  H03F2203/45036 ,  H03F2203/45172 ,  H03F2203/45206 ,  H03F2203/45556 ,  H03F2203/45566 ,  H03F2203/45592 ,  H03F2203/45621 ,  H03F2203/45638 ,  H03F2203/45726 ,  H03F2203/45728 ,  H03F2203/45731 ,  H03F2203/7221 ,  H03F2203/7224 ,  H03H7/48

Abstract: An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.

公开(公告)号：EP2432121B1

公开(公告)日：2014-03-19

申请号：EP10176754.9

申请日：2010-09-15

Applicant: Sony Ericsson Mobile Communications AB

Inventor： Skarp, Filip ,  Zander, Olof

IPC: H03F3/189 ,  H03F1/56 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F3/24 ,  H03F1/56 ,  H03F3/189 ,  H03F3/195 ,  H03F2200/36 ,  H03F2200/387 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421

公开(公告)号：EP2432121A1

公开(公告)日：2012-03-21

申请号：EP10176754.9

申请日：2010-09-15

Applicant: Sony Ericsson Mobile Communications AB

Inventor： Skarp, Filip ,  Zander, Olof

IPC: H03F3/189 ,  H03F1/56

CPC classification number: H03F3/24 ,  H03F1/56 ,  H03F3/189 ,  H03F3/195 ,  H03F2200/36 ,  H03F2200/387 ,  H03F2200/414 ,  H03F2200/417 ,  H03F2200/421

Abstract: The present invention relates to a power amplifier unit (30, 40, 50, 60a-60d, 70) comprising a power amplifier element (31, 41, 51, 71) and a matching unit (32, 42, 52, 72). The unit comprises an impedance matched MicroElectroMechanicalSystem (MEMS) switch element (33, 43, 53, 73) between said power amplifier element (31, 41, 51, 71) and said matching unit (32, 42, 52, 72).

Abstract translation: 本发明涉及包括功率放大器元件（31,41,51,71）和匹配单元（32,42,52,72）的功率放大器单元（30,40,50,60a-60d，70）。 该单元包括位于所述功率放大器元件（31,41,51,71）和所述匹配单元（32,42,52,72）之间的阻抗匹配的微电子机械系统（MEMS）开关元件（33,43,53,73）。

公开(公告)号：EP1714380A2

公开(公告)日：2006-10-25

申请号：EP04779492.0

申请日：2004-07-29

Applicant: MOTOROLA INC., A Corporation of the state of Delaware

Inventor： CONRAD, Clark, W. ,  KLOMSDORF, Armin ,  SCHIRMANN, Ernest

IPC: H03F1/00

CPC classification number: H03F3/211 ,  H03F1/02 ,  H03F1/0211 ,  H03F1/0261 ,  H03F1/0277 ,  H03F1/56 ,  H03F3/72 ,  H03F2200/303 ,  H03F2200/391 ,  H03F2200/417 ,  H03F2203/7227

Abstract: A power amplification circuit (10) includes a scalable power amplifier (20) to produce an RF output signal (50) at an output of the power amplification circuit (10), and a variable impedance circuit (30) coupled to the output of the power amplification circuit (10). The scalable power amplifier (20) includes a plurality of selectively activated amplifier elements (22), (24), (26) to produce the RF output signal (50) in accordance with a desired RF output signal power level. The power amplification circuit (10) selectively activates individual amplifier elements by, for example reducing power or increasing power to at least one amplifier element. The variable impedance circuit (30) varies an impedance of the variable impedance circuit (30) to dynamically load the output of the scalable power amplifier(20).

公开(公告)号：EP1054510A2

公开(公告)日：2000-11-22

申请号：EP00303919.5

申请日：2000-05-10

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Nakano, Kazuhiro, c/o Alps Electric Co., Ltd. ,  Noumi, Hiroki, c/o Alps Electric Co., Ltd.

IPC: H03J5/24

CPC classification number: H03J5/242 ,  H03F3/191 ,  H03F2200/111 ,  H03F2200/417

Abstract: The high frequency tuning amplifier (3) for buffer has a tuning circuit (8) consisting of a serial circuit of the first (20) and second (21) inductors connected between the output of transistor amplifying stage and the power source, a first capacitor (22) connected in parallel to the serial circuit of first and second inductors, a serial circuit of the second (23) and third (24) capacitors connected in parallel to the second inductor and a switching element (26) to which a band switch voltage is supplied, connected between the connecting point of the second and third capacitors and the reference voltage point. The turning circuit is turned to the high band frequency when the switching element is turned ON and to the low band frequency when the switching element is turned OFF.

Abstract translation: 用于缓冲器的高频调谐放大器（3）具有由连接在晶体管放大级的输出端与电源之间的第一（20）和第二（21）电感器的串联电路组成的调谐电路（8），第一电容器 （22）并联连接到第一和第二电感器的串联电路，并联连接到第二电感器的第二（23）和第三（24）电容器的串联电路和一个开关元件（26），频带开关 电压被提供，连接在第二和第三电容器的连接点和参考电压点之间。 当开关元件接通时，转向电路转为高频带频率，当开关元件断开时转向低频带频率。

公开(公告)号：EP3410606A1

公开(公告)日：2018-12-05

申请号：EP18175002.7

申请日：2018-05-30

Applicant: Laird Dabendorf GmbH

Inventor： Nast, Helmut ,  Jacobi, Raimo ,  Sayed, Ahmed

IPC: H04B1/18 ,  H04B1/3877

CPC classification number: H04B7/15528 ,  H03F1/52 ,  H03F3/19 ,  H03F2200/252 ,  H03F2200/417 ,  H03F2200/451 ,  H04B1/18 ,  H04B1/3877

Abstract: Die Erfindung betrifft eine Signalkopplungsvorrichtung zur Übertragung von Sendesignalen zwischen einem Endgerät (2) und einer Antenne (11), wobei die Signalkopplungsvorrichtung (1) eine endgeräteseitige Schnittstelle (4), mindestens eine Dämpfungseinrichtung (5) und mindestens einen Verbindungssignalzweig (6) zur Verbindung der endgeräteseitigen Schnittstelle (4) mit der Dämpfungseinrichtung (5) umfasst, wobei die Signalkopplungsvorrichtung (1) mindestens eine erste Einrichtung (7) zur Sendeaktivitätsdetektion umfasst, wobei die erste Einrichtung (7) zur Sendeaktivitätsdetektion signaltechnisch mit dem Verbindungssignalzweig (6) gekoppelt ist, wobei mittels der ersten Einrichtung (7) zur Sendeaktivitätsdetektion ein Schutzsignal (SS) zur Steuerung der Dämpfungseinrichtung erzeugbar ist, wenn eine Sendeleistung eines Sendesignals höher als eine vorbestimmte Leistung ist, sowie ein Verfahren zum Betrieb einer Signalkopplungsvorrichtung.

公开(公告)号：EP3084958A1

公开(公告)日：2016-10-26

申请号：EP14825002.0

申请日：2014-12-12

Applicant: Qualcomm Incorporated

Inventor： HADJICHRISTOS, Aristotele ,  PRESTI, Calogero Davide ,  NEJATI, Babak

IPC: H03F1/56 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F1/565 ,  H03F3/19 ,  H03F3/191 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/111 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/417 ,  H03F2200/423

Abstract: A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.

Abstract translation: 公开了一种可调加载线。 在示例性实施例中，一种装置包括：放大器，被配置为输出具有所选功率电平的放大信号和耦合以在输入端接收放大信号的第一阻抗网络，并产生具有第一功率电平的第一输出信号 输出端子。 第一阻抗网络被配置为加载放大的信号以将所选择的功率电平转换为第一功率电平。 该装置还包括被配置为选择性地接收第一输出信号并且在第二输出端产生具有第二功率电平的第二输出信号的第二阻抗网络。 第二阻抗网络被配置为与第一阻抗网络组合以加载放大的信号以将所选择的功率电平转换为第二功率电平。