公开(公告)号：EP3394890A1

公开(公告)日：2018-10-31

申请号：EP16820474.1

申请日：2016-12-12

Applicant: Raytheon Company

Inventor： FLETCHER, David R. ,  HESTON, David D.

IPC: H01L23/66 ,  H03F1/18 ,  H03F3/195 ,  H03F3/60

CPC classification number: H03F1/0205 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/665 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/1423 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03F1/0261 ,  H03F1/18 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/607 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/555 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.

公开(公告)号：EP3346546A1

公开(公告)日：2018-07-11

申请号：EP18150228.7

申请日：2018-01-03

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： NDIP, Ivan

IPC: H01Q1/22 ,  H01Q1/44 ,  H01Q9/42 ,  H01Q19/10

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19031 ,  H01P3/08 ,  H01Q1/2283 ,  H01Q1/44 ,  H01Q1/523 ,  H01Q9/42 ,  H01Q15/02 ,  H01Q19/10 ,  H01Q21/0025

Abstract: Die Erfindung betrifft unter anderem eine Antennenvorrichtung (10) mit einem auf einem Substrat (11) angeordneten Hochfrequenz-Chip (12), wobei der Hochfrequenz-Chip (12) mindestens einen Antennenausgangsanschluss (13) aufweist, und der Antennenausgangsanschluss (13) als ein erster Befestigungsbereich (13) für einen elektrischen Leiter dient. Die Antennenvorrichtung (10) weist außerdem einen ersten Bonddraht (14) auf, der den ersten Befestigungsbereich (13) mit einem auf dem Substrat (11) angeordneten zweiten Befestigungsbereich (15) elektrisch leitend verbindet. Außerdem weist die Antennenvorrichtung (10) einen zweiten Bonddraht (16) auf, der den zweiten Befestigungsbereich (15) und einen auf dem Substrat (11) angeordneten dritten Befestigungsbereich (17) elektrisch leitend verbindet. Erfindungsgemäß bilden die beiden elektrisch in Reihe geschalteten ersten und zweiten Bonddrähte (14, 16) eine Antenne bilden. Dabei sind der erste und der zweite Bonddraht (14, 16) zumindest bereichsweise von dem Substrat (11) beabstandet.

公开(公告)号：EP2362417B1

公开(公告)日：2018-01-10

申请号：EP11004204.1

申请日：2009-09-02

Applicant: Linear Technology Corporation

Inventor： Pruitt, David, A.

IPC: H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC classification number: H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

Abstract: A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

公开(公告)号：EP2983291B1

公开(公告)日：2017-12-06

申请号：EP14290235.2

申请日：2014-08-07

Applicant: Ampleon Netherlands B.V.

Inventor： Moronval, Xavier ,  Bouny, Jean-Jacques ,  Bouisse, Gerard

IPC: H03F1/02 ,  H03F3/195 ,  H03F1/56 ,  H03F3/24 ,  H01L23/66

CPC classification number: H03F1/0288 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6644 ,  H03F1/565 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/225 ,  H03F2200/36 ,  H03F2200/391 ,  H03F2200/408

Abstract: A die is described comprising at least one 3-way Doherty amplifier (100) comprising a main stage (120), a first peak stage (130) and a second peak stage(140). An input network (110) includes a first impedance connected to an input of the first peak stage (130) and providing a -90° phase shift and a second impedance connected to an input of the second peak stage (140) and providing a 90° phase shift. An output network (150) includes a third impedance connected to the output of the first peak stage (130) and providing a 180° phase shift and a fourth impedance connected to the output of the main stage (120) and providing a 90° phase shift.

公开(公告)号：EP2722882A3

公开(公告)日：2017-12-06

申请号：EP13183320.4

申请日：2013-09-06

Applicant: NXP USA, Inc.

Inventor： Viswanathan, Lakshminarayan ,  Jones, Jeffrey ,  Marshall, Scott D.

IPC: H01L23/66 ,  H01L23/047

CPC classification number: H01L23/66 ,  H01L23/047 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of semiconductor devices (100, 300, 600, 700, 800, 900, 1100) (e.g., RF devices) include a substrate (306, 606, 706, 806, 906, 1106), an isolation structure (308, 608, 708, 808, 908, 1108), an active device (120, 320, 620, 720, 820, 920, 1120), a lead (104, 304, 604, 704, 804, 904, 1104), and a circuit (149, 150, 349, 350, 649, 650, 749, 750, 849, 850, 949, 950). The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements (136, 138, 144, 146, 338, 344, 638, 644, 738, 744, 838, 844, 846, 936, 938, 944, 946, 1136, 1146) positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit (149, 349, 649, 749, 849, 949) and/or an impedance matching circuit (150, 350, 650, 750, 850, 950). Embodiments also include method (1202, 1204, 1206, 1208, 1210) of manufacturing such semiconductor devices.

Abstract translation: 半导体器件（100,300,600,700,800,900,1100）（例如，RF器件）的实施例包括衬底（306,606,706,806,906,1106），隔离结构（308,608， （例如，708,808,908,1108），有源器件（120,320,620,720,820,920,1120），引线（104,304,604,704,804,904,1104）和电路（ 149，150，349，350，649，650，749，750，849，850，949，950）。 隔离结构耦合到衬底，并且包括开口。 有源器件区域由通过开口暴露的衬底表面的一部分限定。 有源器件耦合到有源器件区域内的衬底表面。 电路电耦合在有源器件和引线之间。 该电路包括位于有源器件外部的一个或多个元件（136,138,144,146,338,344,638,644,738,744,838,844,846,936,938,944,946,1136,1146） 器件区域（例如，物理耦合到隔离结构和/或在引线下）。 位于有源器件区域外的元件可以包括包络终端电路（149,349,649,749,849,949）和/或阻抗匹配电路（150,350,650,750,850,950）的元件。 实施例还包括制造这种半导体器件的方法（1202,1204,1206,1208,1210）。

公开(公告)号：EP3179630A1

公开(公告)日：2017-06-14

申请号：EP16185106.8

申请日：2016-08-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takagi, Kazutaka

IPC: H03F3/189 ,  H03F3/19 ,  H01L23/66 ,  H01L25/07 ,  H01L25/16

CPC classification number: H01L23/66 ,  H01L25/072 ,  H01L25/16 ,  H01L25/162 ,  H01L29/1602 ,  H01L29/1608 ,  H01L2223/66 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6683 ,  H01L2224/40 ,  H01L2224/49175 ,  H03F3/195

Abstract: A high frequency semiconductor amplifier includes an input circuit (20), an output circuit (30), a first semiconductor element (40), and a package. The input circuit (20) includes a first DC blocking capacitor (27), an input transmission line (22), a first input pad part (23) connected to the input transmission line (22), and a first bias circuit (26). The output circuit (30) includes a first output pad part (33), a second DC blocking capacitor (37), an output transmission line (32), and a second bias circuit (36). The first semiconductor element (40) includes a nitride-based semiconductor layer and is arranged between the input circuit (20) and the output circuit (30). The first semiconductor element (40), the input circuit (20) and the output circuit are bonded to the package. The first bias circuit (26) includes a first grounded capacitor (24) and a first transmission line (25). The second bias circuit (36) includes a second grounded capacitor (34) and a second transmission line (35).

Abstract translation: 高频半导体放大器包括输入电路（20），输出电路（30），第一半导体元件（40）和封装。 输入电路20包括第一隔直流电容器27，输入传输线22，与输入传输线22连接的第一输入端子部23以及第一偏置电路26， 。 输出电路30包括第一输出焊盘部分33，第二DC阻塞电容器37，输出传输线路32和第二偏置电路36。 第一半导体元件（40）包括氮化物基半导体层并且布置在输入电路（20）和输出电路（30）之间。 第一半导体元件（40），输入电路（20）和输出电路被接合到封装。 第一偏置电路（26）包括第一接地电容器（24）和第一传输线（25）。 第二偏置电路（36）包括第二接地电容器（34）和第二传输线（35）。

公开(公告)号：EP3159831A1

公开(公告)日：2017-04-26

申请号：EP15190726.8

申请日：2015-10-21

Applicant: NXP B.V.

Inventor： Zenz, Christian

IPC: G06K19/077

CPC classification number: G06K19/07754 ,  G06K19/07769 ,  H01L21/4853 ,  H01L23/49838 ,  H01L23/49855 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2224/48227 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: The disclosure relates to a dual-interface integrated circuit (IC) card. Embodiments disclosed include a dual-interface card (100) comprising: a card body (122) containing an antenna (120), the antenna having first and second antenna connections; and a dual-interface integrated circuit card module (150) comprising: a substrate (104) having first and second opposing surfaces; a contact area (102) on the first surface of the substrate (104), the contact area (102) comprising a plurality of contact pads (108) and first and second routing connections (106) each having a first end and a second end; an integrated circuit (110) on the second surface of the substrate (104); electrical connections through the substrate (104) connecting the integrated circuit (110) to the plurality of contact pads (108) and to the first end of each of the first and second routing connections (106); and first and second antenna connectors (118) disposed in respective first and second holes (103) in the substrate (104) and in electrical contact with the second end of the respective first and second routing connections, wherein the first and second antenna connectors (118) of the card module are electrically connected to the first and second antenna connections of the card body (122).

Abstract translation: 本公开涉及一种双接口集成电路（IC）卡。 所公开的实施例包括双接口卡（100），包括：包含天线（120）的卡体（122），所述天线具有第一和第二天线连接; 以及双接口集成电路卡模块（150），包括：具有第一和第二相对表面的基板（104） 所述接触区域（102）在所述基底（104）的所述第一表面上，所述接触区域（102）包括多个接触垫（108）和第一和第二路由连接（106），每个具有第一端和第二端 ; 在衬底（104）的第二表面上的集成电路（110）; 通过将集成电路（110）连接到多个接触焊盘（108）的基板（104）和第一和第二路由连接（106）中的每一个的第一端的电连接; 以及设置在所述基板（104）中的相应的第一和第二孔（103）中并与相应的第一和第二路由连接的第二端电接触的第一和第二天线连接器（118），其中所述第一和第二天线连接器 卡模块的电路118（118）电连接到卡体（122）的第一和第二天线连接。

公开(公告)号：EP3151273A1

公开(公告)日：2017-04-05

申请号：EP16194094.5

申请日：2014-12-03

Applicant: NXP USA, Inc.

Inventor： SZYMANOWSKI, Margaret A. ,  MUSA, Sarmad K ,  SANTOS, Fernando A ,  SHAH, Mahesh K.

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device (20) that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate (74) on which a first circuit (22) and a second circuit (24) are formed proximate to each other. An isolation wall (50) of electrically conductive material is located between the first circuit and the second circuit, the isolation wall (50) being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. The isolation wall (50) includes a plurality of holes (52) through which encapsulation material may flow during a process of making the semiconductor device (10). Several types of isolation wall (50) are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件（20）的系统和方法。 半导体器件具有基板（74），第一电路（22）和第二电路（24）彼此靠近地形成在其上。 导电材料的隔离壁（50）位于第一电路和第二电路之间，隔离壁（50）构造成在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 隔离壁（50）包括多个孔（52），在制造半导体器件（10）的过程中，封装材料可以通过该孔（52）流动。 提出了几种类型的隔离墙（50）。

公开(公告)号：EP2237316A4

公开(公告)日：2017-03-01

申请号：EP09706254

申请日：2009-01-30

Applicant: KYOCERA CORP

Inventor： TSUJINO MAHIRO

IPC: H01L23/498 ,  H01L23/02 ,  H01L23/04 ,  H01L23/12

CPC classification number: H01L23/49833 ,  H01L23/057 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A connector which can be made compact is provided. A package and an electronic device which can be made compact by using the connector are also provided. The connector has a first conductor and a second conductor for connecting an internal circuit formed in a frame-shaped container and an external circuit provided outside of the container, comprising: a stacked body comprising a plurality of dielectric layers and having a first top surface, a second top surface positioned at a height different from that of the first top surface and a bottom surface positioned opposite to the second top surface; a first conductor comprising a first external connecting terminal disposed on the first top surface of the stacked body and for connecting to the external circuit, and a first internal connecting terminal disposed on the first top surface of the stacked body and for connecting to the internal circuit; and a second comprising a second internal connecting terminal disposed on the second top surface and for connecting to the internal circuit, and a second external connecting terminal disposed on the bottom surface and for connecting to the external circuit.

公开(公告)号：EP3086469A4

公开(公告)日：2016-12-21

申请号：EP14877106

申请日：2014-01-06

Applicant: HUAWEI TECH CO LTD

Inventor： ZHANG XIAOMIN ,  SU YONGGE ,  JIAO LIUYAN

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H03F3/60

CPC classification number: H03F1/0288 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6655 ,  H03F3/195 ,  H03F3/245 ,  H03F3/607 ,  H03F2200/423 ,  H03F2200/451

Abstract: Embodiments of the present invention relate to a Doherty power amplifier that includes a main power amplification circuit, an auxiliary power amplification circuit, a connection circuit, and an impedance conversion circuit, where an output end of the main power amplification circuit and an output end of the auxiliary power amplification circuit are connected to two ends of the connection circuit separately by using bonding wires, the output end of the auxiliary power amplification circuit is further connected to one end of the impedance conversion circuit by using a bonding wire, and the other end of the impedance conversion circuit is connected to an output load. In the embodiments of the present invention, an impedance conversion circuit is formed by directly connecting parasitic capacitors Cds between drains and sources of dies in two power transistors and a PCB, so that an output matching circuit in an existing Doherty power amplifier can be removed, thereby achieving an effect of reducing an area of the Doherty power amplifier.

Abstract translation: 本发明的实施例涉及一种Doherty功率放大器，其包括主功率放大电路，辅助功率放大电路，连接电路和阻抗转换电路，其中主功率放大电路的输出端和输出端 辅助功率放大电路通过使用接合线分别连接到连接电路的两端，辅助功率放大电路的输出端通过使用接合线进一步连接到阻抗转换电路的一端，另一端 的阻抗转换电路连接到输出负载。 在本发明的实施例中，通过在两个功率晶体管和PCB之间直接连接漏极和管芯源极之间的寄生电容器Cds来形成阻抗转换电路，从而可以去除现有Doherty功率放大器中的输出匹配电路， 从而实现减少Doherty功率放大器的面积的效果。