公开(公告)号：EP3168989A1

公开(公告)日：2017-05-17

申请号：EP16768108.9

申请日：2016-01-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： MASUDA Hiroshi

IPC: H03H7/01 ,  H01F17/00 ,  H01F27/00

CPC classification number: H03H7/0115 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/004 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1733 ,  H03H7/1766 ,  H03H2001/0085

Abstract: An object of the present invention is to provide a low pass filter that allows the interval between attenuation poles to be easily adjusted.
A low pass filter according to the present invention includes: a first via-hole conductor connected to a first end portion of a first inductor and a third end portion of a second inductor and extending to another side in a lamination direction with respect to a second end portion of the first inductor and a fourth end portion of the second inductor; and a first capacitor connected in parallel with at least a portion of the first inductor and a portion of the second inductor and formed by a first capacitor conductor layer.

Abstract translation: 本发明的一个目的是提供一种低通滤波器，其允许容易地调节衰减极点之间的间隔。 根据本发明的低通滤波器包括：第一过孔导体，其连接到第一电感器的第一端部和第二电感器的第三端部，并且在相对于第二电感器的层压方向的另一侧延伸 所述第一电感器的第一端部和所述第二电感器的第四端部; 以及与第一电感器的至少一部分和第二电感器的一部分并联连接并由第一电容器导体层形成的第一电容器。

公开(公告)号：EP3005561A1

公开(公告)日：2016-04-13

申请号：EP14733447.8

申请日：2014-05-27

Applicant: Newlans, Inc.

Inventor： GUPTA, Dev, V. ,  LAI, Zhiguo ,  NOHRA, George ,  MADAN, Anuj

IPC: H03H7/38 ,  H03H7/12

CPC classification number: H01F17/0013 ,  H01F2017/0026 ,  H01G4/38 ,  H01G4/40 ,  H01G5/38 ,  H01L23/642 ,  H01L27/0811 ,  H01L28/10 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/83385 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03H5/003 ,  H03H7/01 ,  H03H7/0115 ,  H03H7/0138 ,  H03H7/0153 ,  H03H7/09 ,  H03H7/38 ,  H03H7/48 ,  H03H11/1291 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2240/00 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors (121,122,123,124) implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages (VBl, VB2) for biasing the MOS capacitors of the MOS variable capacitor cells, such that the voltage coefficient of capacitance is kept low and non-linearities in the circuit are reduced.

Abstract translation: 电感器部件包括多个导电元件，每个导电元件形成为导电材料的单独贴片，其中导电元件布置成垂直堆叠并彼此紧密耦合。 电介质设置在更相邻的导电元件之间，电介质具有介电常数并且足够薄，以便在相邻的导电元件之间提供至少一半以上的互感因数。 电介质通常比相邻的导体薄。

公开(公告)号：EP3005560A1

公开(公告)日：2016-04-13

申请号：EP14710166.1

申请日：2014-02-26

Applicant: Newlans, Inc.

Inventor： GUPTA, Dev V. ,  LAI, Zhiguo

IPC: H03H7/38 ,  H01L23/64 ,  H01L27/08 ,  H01G4/38

CPC classification number: H01F17/0013 ,  H01F2017/0026 ,  H01G4/38 ,  H01G4/40 ,  H01G5/38 ,  H01L23/642 ,  H01L27/0811 ,  H01L28/10 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/83385 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03H5/003 ,  H03H7/01 ,  H03H7/0115 ,  H03H7/0138 ,  H03H7/0153 ,  H03H7/09 ,  H03H7/38 ,  H03H7/48 ,  H03H11/1291 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2240/00 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A highly linear, variable capacitor array (400) constructed from multiple cells (100-0, 100_ 1,... 100_ N). Each cell includes a pair of passive, two-terminal capacitor components connected in antiparallel. The capacitor components may be Metal Oxide Semicondutor, MOS, capacitors. A control circuit (410) applies bias voltages (411_0, 411 1,... 411_ N) to bias voltage terminals associated with each capacitor component, to thereby control the overall capacitance of the array. The two capacitors in each cell are connected in anti-parallel to reduce the cell's and the array's voltage coefficient of capacitance. MOS capacitors are preferably operated in inversion or accumulation mode.

公开(公告)号：EP3005558A1

公开(公告)日：2016-04-13

申请号：EP14714439.8

申请日：2014-02-26

Applicant: Newlans, Inc.

Inventor： GUPTA, Dev V. ,  LAI, Zhiguo ,  MOUSSA, Mehdi Si

IPC: H03H7/01

CPC classification number: H01F17/0013 ,  H01F2017/0026 ,  H01G4/38 ,  H01G4/40 ,  H01G5/38 ,  H01L23/642 ,  H01L27/0811 ,  H01L28/10 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/83385 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03H5/003 ,  H03H7/01 ,  H03H7/0115 ,  H03H7/0138 ,  H03H7/0153 ,  H03H7/09 ,  H03H7/38 ,  H03H7/48 ,  H03H11/1291 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2240/00 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A signal handler providing high linearity in a small size, applicable across wide operating frequencies and bandwidths, while also adapted to preferred integrated circuit (IC) and printed circuit board technologies. In one implementation, a signal handling apparatus (100) includes an input impedance transformer (102) for receiving an input signal and matching an internal apparatus impedance, a splitter (104) for providing N split signals, a number of signal processing circuits (110; 112-1,..., 112-m) for processing the N split signals, a combiner (120) for combining the N split signals into a combined signal, and output impedance transformer (122) for receiving the combined signal and for matching the internal apparatus impedance to an output impedance of the apparatus. The apparatus may provide filtering, duplexing and other radio frequency signal processing functions. A tunable duplexer may be implemented using a vector inductor and tunable capacitor array with frequency dependent impedance transformers.

公开(公告)号：EP2544368A3

公开(公告)日：2013-04-24

申请号：EP12175435.2

申请日：2012-07-06

Applicant: Kemet Electronics Corporation

Inventor： Bultitude, John ,  Laps, Mark R. ,  Magee, James R. ,  Jones, Lonnie G.

IPC: H03H1/00 ,  H03H3/00 ,  H03H7/01 ,  H01P1/20 ,  H01F17/00 ,  H01F41/04 ,  H01G4/40

CPC classification number: H03H7/0115 ,  H01F41/046 ,  H01F2017/0026 ,  H01G4/40 ,  H01P1/20345 ,  H03H1/0007 ,  H03H3/00 ,  H03H9/00 ,  H03H2001/0085 ,  Y10T29/4913

Abstract: An improved electronic filter is provided with capacitance and integral inductance properties. The filter has a capacitor with first planar internal electrodes in electrical contact with a first termination and second planar internal electrodes in electrical contact with a second termination. A dielectric is between the first planar internal electrodes and the second planer internal electrodes. A third termination is provided and a conductive trace on a surface of the capacitor is between the third termination and the first termination. A ferromagnetic or ferrimagnetic material is coupled to the conductive trace. Sintering of the capacitor can be followed by formation of the components with inductance properties.

Abstract translation: 改进的电子滤波器具有电容和积分电感特性。 滤波器具有电容器，其具有与第一端接电接触的第一平面内部电极和与第二端接电接触的第二平面内部电极。 电介质在第一平面内部电极和第二平面内部电极之间。 提供第三终端，并且电容器表面上的导电迹线在第三终端和第一终端之间。 铁磁或铁磁材料耦合到导电迹线。 电容器的烧结之后可以形成具有电感特性的元件。

公开(公告)号：EP2200179A1

公开(公告)日：2010-06-23

申请号：EP08841023.8

申请日：2008-09-11

Applicant: Murata Manufacturing Co. Ltd.

Inventor： ISHOSHIMA, Tomoshiro

IPC: H03H7/09 ,  H03H7/075 ,  H01F17/00 ,  H01F27/00 ,  H01G4/12 ,  H01G4/30 ,  H01G4/40

CPC classification number: H03H7/0115 ,  H01F2017/0026 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H01P1/20345 ,  H03H7/09 ,  H03H7/1725 ,  H03H7/1791 ,  H03H2001/0085

Abstract: There is provided a multilayer electronic component and a multilayer electronic component manufacturing method capable of easily controlling the degree of magnetic field coupling between inductors. Via-hole conductors (54, 62) are formed so that they extend in a lamination direction in a laminate (12), and function as a first inductor. Via-hole conductors (56, 64) are formed so that they extend in the lamination direction in the laminate (12), and function as a second inductor. A first capacitor and the first inductor form a first resonance circuit. A second capacitor and the second inductor form a second resonance circuit. The via-hole conductors (54, 56) are formed in a first insulating layer so that they are apart from each other by a first distance D1. The via-hole conductors (62, 64) are formed in a second insulating layer so that they are apart from each other by a second distance D2.

Abstract translation: 提供了能够容易地控制电感器之间的磁场耦合度的多层电子部件和多层电子部件制造方法。 通孔导体（54,62）形成为使得它们在叠层（12）中沿层叠方向延伸，并且用作第一电感器。 通孔导体（56,64）形成为使得它们在层叠体（12）中沿层叠方向延伸，并且用作第二电感器。 第一电容器和第一电感器形成第一谐振电路。 第二电容器和第二电感器形成第二谐振电路。 通孔导体（54,56）形成在第一绝缘层中，使得它们彼此分开第一距离D1。 通孔导体（62,64）形成在第二绝缘层中，使得它们彼此分开第二距离D2。

公开(公告)号：EP1884963A1

公开(公告)日：2008-02-06

申请号：EP06731042.5

申请日：2006-04-04

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： FUJIKI, Yasuhiro c/o Murata Manufacturing Co., Ltd ,  ISHIDA, Kosuke c/o Murata Manufacturing Co., Ltd.

IPC: H01F17/00 ,  H01F19/06

CPC classification number: H01F37/00 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/065 ,  H01F2017/067 ,  H03H7/48

Abstract: A multilayer directional coupler which is easy to mass-produce and reduce in size, in which fine setting of the degree of electromagnetic coupling is facilitated, and which has a large bandwidth ratio is provided.
A multilayer directional coupler 1 includes magnetic substrates 2-1 and 2-2, a laminate 3 including first and second transformers 5 and 6, and external electrodes 4-1 to 4-6. The electrode 4-2, which is connected to two ends of a primary coil 5-1 of the first transformer 5, is used as an input end for a main signal, and the electrode 4-1 is used as an output end. The electrode 4-3, which is connected to two ends of a secondary coil 6-2 of the second transformer 6, is used as an output end for a subsignal. A winding length ratio N1 (N2) of secondary coil 5-2 (6-1) to the primary coil 5-1 (6-2) is set to be greater than 1 and not greater than 10. Preferably, the ratio N2/N1 is set to be greater than 0.5 and less than 2.0.

Abstract translation: 提供了易于批量生产和减小尺寸的多层定向耦合器，其中便于电磁耦合程度的精细设置，并且具有大带宽比。 多层定向耦合器1包括磁性基板2-1和2-2，包括第一和第二变压器5和6的层叠体3和外部电极4-1至4-6。 连接到第一变压器5的初级线圈5-1的两端的电极4-2用作主信号的输入端，电极4-1用作输出端。 连接到第二变压器6的次级线圈6-2的两端的电极4-3用作子信号的输出端。 次级线圈5-2（6-1）与初级线圈5-1（6-2）的绕组长度比N1（N2）被设定为大于1且不大于10.优选地，比率N2 / N1设定为大于0.5且小于2.0。

公开(公告)号：EP1770074A2

公开(公告)日：2007-04-04

申请号：EP06020576.2

申请日：2006-09-29

Applicant: TDK Corporation

Inventor： Umeda, Hidenobu, c/o TDK Corporation ,  Takahashi, Yukio, c/o TDK Corporation

IPC: C04B35/26 ,  H01C7/108 ,  H01C7/18 ,  C04B35/30 ,  C04B35/38

CPC classification number: H01F17/04 ,  C04B35/2625 ,  C04B35/265 ,  C04B35/2658 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3232 ,  C04B2235/3244 ,  C04B2235/3256 ,  C04B2235/3258 ,  C04B2235/3265 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3284 ,  C04B2235/3293 ,  C04B2235/3298 ,  C04B2235/3418 ,  C04B2235/6025 ,  C04B2235/727 ,  C04B2235/77 ,  C04B2235/83 ,  C04B2235/96 ,  H01F17/0013 ,  H01F27/40 ,  H01F2017/0026 ,  Y10T428/31678

Abstract: In the nonmagnetic Zn-ferrite of the present invention comprising iron oxide and zinc oxide, the content of Fe 2+ is specifically limited. Alternately in the nonmagnetic Zn-ferrite comprising iron oxide and zinc oxide as main components, a given amount of at least one metal oxide selected from the group consisting of manganese oxide, nickel oxide and magnesium oxide is contained. It is thus possible to provide a nonmagnetic Zn-ferrite that can have high resistivity without containing Cu.

Abstract translation: 在包含氧化铁和氧化锌的本发明的非磁性Zn-铁氧体中，Fe 2+的含量被特别限制。 另外，作为主成分的含有氧化铁和氧化锌的非磁性Zn-铁氧体，含有选自氧化锰，氧化镍，氧化镁中的至少一种以上的金属氧化物。 因此，可以提供在不含Cu的情况下可以具有高电阻率的非磁性Zn-铁氧体。

公开(公告)号：EP1654763A1

公开(公告)日：2006-05-10

申请号：EP04774129.3

申请日：2004-07-15

Applicant: Innochips Technology Co., Ltd. ,  Park, In-Kil ,  Hwang, Soon-Ha ,  Kim, Duk-Hee

Inventor： Park, In-Kil ,  Hwang, Soon-Ha ,  Kim, Duk-Hee

IPC: H01L27/02

CPC classification number: H01G4/40 ,  H01C1/148 ,  H01C7/008 ,  H01C7/18 ,  H01C13/02 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/0026 ,  H01G4/232 ,  H01G4/35 ,  H03H1/02 ,  H03H2001/0014 ,  H03H2001/0085 ,  H03H2001/0092

Abstract: The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More p articularly, t he present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to control capacitance and/or inductance of the laminated chip element to a desired value. There is provided a laminated chip element, comprising at least one first sheet on which first and second conductive patterns are formed, the first and second conductive patterns being spaced apart from each other in a direction of both ends of the first sheet; and at least one second sheet on which a third conductive pattern is formed, the third conductive pattern being formed in a transverse direction of both the ends of the first sheet; wherein one ends of the first and second conductive patterns are connected to first and second external terminals, respectively, at least one end of the third conductive pattern is connected to a third external terminal, and the first and second sheets are laminated. There is also provided a laminated chip element, comprising: at least one first sheet on which a first conductive pattern is formed, the first conductive pattern consisting of first to third portions, the first and second portions being spaced apart from each other in a direction of both ends of the first sheet, the second portion connecting the first and second portions to each other to have a predetermined inductance; and at least one second sheet on which a second conductive pattern is formed in a transverse direction of both the ends of the first sheet; wherein the first and second portions are connected to first and second external terminals, respectively, at least one ends of the second conductive pattern is connected to a third external terminal, and the first and second sheets are laminated.

公开(公告)号：EP2887364B1

公开(公告)日：2017-06-07

申请号：EP13290318.8

申请日：2013-12-18

Applicant: NXP B.V.

Inventor： Tesson, Olivier

IPC: H01F17/00 ,  H01F27/28

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0026 ,  H01F2017/0086 ,  H01F2027/2809