摘要:
The invention concerns a power switching circuit (1) comprising - a planar transformer (2) having a primary winding (2a) and a secondary winding (2b), - a power switch (3) having a control gate (4) in electrical connection with the secondary winding (2b), - a switching element (5) configured to provide switching on and off of an electrical current in the primary winding (2a) of the transformer (2), - flyback switching circuitry (6) configured to, in response to a control signal (17), send a turn-on electrical pulse by: - controlling the switching element (5) to switch on, to build up a current in the primary winding (2a), and - controlling the switching element (5) to switch off, to dump the energy stored in the transformer (2) in the secondary winding (2b) inducing the turn-on electrical pulse in the control gate (4) turning the power switch (3) on. The invention also concerns a machine or device incorporating a power switching circuit and a method for driving a control gate of a power switch.
摘要:
An improved solenoid driver control circuit is disclosed in which solenoid current is sensed and provided as an input to a comparator means comprising two separate comparators (24, 25). The comparator means receives a solenoid current sense signal (45) and maximum and minimum reference threshold levels which determine maximum and minimum current limits (I max , I min ;.H max , H min ) for solenoid current during initial pull-in excitation and subsequent hold excitation. Pull-in time (T₁) is defined by a monostable multivibrator (33) reacting to a control pulse (41) to produce a predetermined pull-in time pulse (43) such that the pull-in time is independent of sensed solenoid current. During pull-in time a boost driver switch (53) applies high boost voltage to a power source terminal (16) which supplies solenoid current, and in response to achieving the maximum pull-in current limit (I max ) lower battery voltage is provided at the power source terminal. If the maximum pull-in current limit does not occur within a predetermined time (t b1 ) after pull-in initiation (at t₀), then the lower battery voltage is applied to the power source terminal at that time. The above configuration insures rapid initial solenoid response while minimizing power dissipation and circuit stress.
摘要:
A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.
摘要:
A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.
摘要:
To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage (VP) is applied to a power supply application area (AR_VP). A high side area (AR_HVBK) is formed with a circuit which includes a driver driving a high side transistor (HA) and is operated at a boot power supply voltage (VB) with a floating voltage (VS) as a reference. A low side area (AR_LVBK) is formed with a circuit operated at a power supply voltage (VCC) with a low potential side power supply voltage (COM) as a reference. A first termination area (AR_TRMBK1) is disposed in a ring form so as to surround the power supply application area. A second termination area (AR_TRMBK2) is disposed in a ring form so as to surround the high side area.
摘要:
Die Erfindung betrifft eine Schaltungsanordnung (51; 61; 71), aufweisend: - einen ersten elektronischen Schalter (T 1 ), der im eingeschalteten Zustand des elektronischen Schalters (T 1 ) lediglich elektrischen Strom in einer Stromflussrichtung, jedoch nicht in der entgegengesetzten Stromflussrichtung passieren lässt, insbesondere einen IGBT, - zumindest Teile eines ersten Stromkreises, in dem während dem Betrieb der Anordnung bei eingeschaltetem erstem elektronischem Schalter (T 1 ) ein elektrischer Strom durch den ersten elektronischen Schalter (T 1 ) fließt, - eine erste Steuerung zum Ein- und Ausschalten des ersten elektronischen Schalters (T 1 ), wobei die erste Steuerung ausgestaltet ist, den ersten elektronischen Schalter (T 1 ) wiederholt ein- und auszuschalten, - einen steuerbaren Zusatzschalter (15), der durch die erste Steuerung oder durch eine zusätzliche zweite Steuerung steuerbar ist,
wobei die erste Steuerung und die Steuerung des Zusatzschalters (15) derart ausgestaltet sind, dass der erste elektronische Schalter (T 1 ) erst dann ausgeschaltet wird und der Zusatzschalter (15) erst dann eingeschaltet wird, wenn der Strom durch den ersten elektronischen Schalter (T 1 ) kleiner als 10 % eines Strom- Maximalwertes ist, den der Strom zuvor erreicht hat, wobei der Strom nach dem Verlassen des Strom-Maximalwertes stetig abgenommen hat, und wobei durch Einschalten des Zusatzschalters (15) Ladungsträger, die in dem ersten elektronischen Schalter (T 1 ) nach dessen Ausschalten verblieben sind, aus diesem ausgeräumt werden.
摘要:
Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.