公开(公告)号：EP2049968B1

公开(公告)日：2019-07-10

申请号：EP07794752.1

申请日：2007-05-10

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat ,  YANG, Yun

IPC: G06F1/32

公开(公告)号：EP2748850B1

公开(公告)日：2018-08-22

申请号：EP12753343.8

申请日：2012-08-22

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: H01L25/18 ,  H01L25/10 ,  H01L23/498 ,  H01L23/13 ,  H01L21/60 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L27/108 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package comprises a first memory die (458-1) having a first set of connections, a second memory die (458-2) arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate (470) having a first opening (472-1) and a second opening (472-2), the first substrate having a third set of connections to connect (474-1) to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect (474-2) to the second set of connections of the second memory die via the second opening, and a second substrate (456) having a first integrated circuit (454) disposed thereon. The first substrate is connected (460-2) to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.

公开(公告)号：EP3002874A1

公开(公告)日：2016-04-06

申请号：EP15188986.2

申请日：2006-10-31

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: H03F3/45 ,  H03F3/26

CPC classification number: H03F3/45183 ,  H03F1/08 ,  H03F3/26 ,  H03F2200/36

Abstract: An amplifier circuit includes a first transistor having a control terminal that receives a first amplifier input, a first terminal, and a second. The amplifier circuit includes a transimpedance amplifier having an input that communicates with the first terminal of the first transistor, and an output. The amplifier circuit includes an output amplifier having an input that communicates with the output of the transimpedance amplifier and an output.

Abstract translation: 放大器电路包括具有接收第一放大器输入的控制端子的第一晶体管，第一端子和第二端子。 放大器电路包括跨阻放大器，其具有与第一晶体管的第一端连通的输入端和输出端。 放大器电路包括具有与跨阻放大器的输出通信的输入和输出的输出放大器。

公开(公告)号：EP2082562B1

公开(公告)日：2013-04-10

申请号：EP07839605.8

申请日：2007-10-16

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: H04W52/02 ,  H04M1/725

CPC classification number: G06F1/3231 ,  G06F1/3203 ,  H04M1/22 ,  H04M1/6016 ,  H04M1/67 ,  H04M1/72569 ,  H04M1/72572 ,  H04M2250/10 ,  H04M2250/12 ,  H04M2250/52 ,  H04W52/0254 ,  H04W52/0267 ,  H04W52/027 ,  Y02D10/173 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164

Abstract: A cellular phone comprises a transceiver that wirelessly transmits and receives wireless cellular signals, a display, an input device, a microphone that generates audio signals and a light sensing module that senses ambient light. A control module communicates with the transceiver, the display, the input device, the microphone and the light sensing module, and comprises a comparing module that generates a first signal when the ambient light signal is less than a threshold, a timing module that determines a duration of the first signal and a selecting module that communicates with the timing module and that selectively deactivates the display and the input device when the duration is greater than a first period.

公开(公告)号：EP2030237A2

公开(公告)日：2009-03-04

申请号：EP07809055.2

申请日：2007-05-08

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0203 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41758 ,  H01L29/4238

Abstract: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.

公开(公告)号：EP2100334B1

公开(公告)日：2016-04-13

申请号：EP07866042.0

申请日：2007-12-26

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat ,  KRISHNAMOORTHY, Ravishanker

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7835

公开(公告)号：EP2742649B1

公开(公告)日：2015-06-03

申请号：EP12751206.9

申请日：2012-08-10

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat ,  DANIEL, Tsahi ,  MELTS, Dimitry

IPC: H04L12/28 ,  H04L29/06

CPC classification number: H04L63/02 ,  H04L12/2878 ,  H04L63/105 ,  H04L63/162

公开(公告)号：EP2792215A1

公开(公告)日：2014-10-22

申请号：EP12819157.4

申请日：2012-12-14

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat ,  KRISHNAMOORTHY

IPC: H05B33/08

CPC classification number: H05B33/086 ,  F21K9/64 ,  H05B33/0827 ,  H05B33/083 ,  H05B33/0845 ,  H05B33/0857 ,  H05B33/0863 ,  H05B33/0866 ,  H05B37/02

Abstract: A system including a first transistor, a second transistor, and a comparator. The first transistor is configured to supply a first current to a first load connected to a first terminal of the first transistor. The second transistor is configured to supply a second current to a second load connected to a first terminal of the second transistor, wherein the first current and the second current have a predetermined ratio. The comparator is configured to compare a voltage at the first terminal of the first transistor or a voltage at the first terminal of the second transistor to a reference voltage, and to adjust, based on the comparison, biasing of the first transistor and the second transistor to maintain the predetermined ratio between the first current and the second current.

Abstract translation: 一种包括基部的系统，其包括第一组和第二组发光二极管（LED），以在蓝光光谱中的第一和第二波长范围内发射具有第一和第二波长的第一和第二波长的蓝光;布置在第二预定 距离基部的距离，以及在玻璃层的面向LED的表面上以交替图案排列的具有预定长度的第一和第二荧光体的多个涂层。 第一组和第二组的LED以交替图案布置在基部上并且彼此分开第一预定距离。 第一和第二荧光体的涂层的中心分别与第一和第二组中的相应LED的中心对准。

公开(公告)号：EP2596680A1

公开(公告)日：2013-05-29

申请号：EP12737636.6

申请日：2012-06-18

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat ,  SUTARDJA, Pantas ,  ZHANG, Wanfeng ,  CHOI, Jinho

IPC: H05B33/08

CPC classification number: H05B33/0815 ,  H02M3/33507 ,  H05B33/0851

Abstract: A triac dimming system for solid-state loads, LEDs, is based on a flyback DC/DC converter and includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a PWM switching circuit. The second coil is configured to generate a first current based on the first voltage to power the solid-state load. The system also includes a third coil. The third coil is configured to generate a second supply voltage based on the first voltage. A bleeder module includes a PWM controlled switch and is connected to the secondary load side of the transformer.

Abstract translation: 一个系统包括一个变压器。 变压器包括第一线圈和第二线圈。 第一线圈被配置为基于开关电路的输出接收第一电压。 第二线圈被配置为基于第一电压产生第一电流以对固态负载供电。 该系统还包括第三线圈。 第三线圈被配置为基于第一电压产生第二电压。

公开(公告)号：EP2030237B1

公开(公告)日：2011-02-09

申请号：EP07809055.2

申请日：2007-05-08

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0203 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41758 ,  H01L29/4238

Abstract: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the drain. The first and second gates are arranged farther apart in the first regions than in the second regions.