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164 条记录 (耗时 0.022 秒)

    ADAPTIVE CONTROL CIRCUIT OF STATIC RANDOM ACCESS MEMORY
    1.
    发明公开
    ADAPTIVE CONTROL CIRCUIT OF STATIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：EP4198984A1

    公开(公告)日：2023-06-21

    申请号：EP22210449.9

    申请日：2022-11-30

    申请人： MediaTek Inc.

    发明人： WANG, Dao-Ping

    IPC分类号： G11C11/417

    摘要： An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.

    ELECTRONIC CIRCUIT AND BISTABLE CIRCUIT
    2.
    发明公开
    ELECTRONIC CIRCUIT AND BISTABLE CIRCUIT 审中-公开

    公开(公告)号：EP3979499A1

    公开(公告)日：2022-04-06

    申请号：EP20812785.2

    申请日：2020-03-18

    申请人： Japan Science and Technology Agency

    发明人： SUGAHARA, Satoshi ,  KITAGATA, Daiki ,  YAMAMOTO, Shuichiro

    IPC分类号： H03K3/356 ,  G11C14/00 ,  G11C11/412 ,  G11C11/417

    摘要： Provided is an electronic circuit including a cell array including memory cells each including a bistable circuit that includes a first inverter circuit and a second inverter circuit, each of the first inverter circuit and the second inverter circuit having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in transfer characteristics, wherein each of the first inverter circuit and the second inverter circuit are configured to be switchable between the first mode and the second mode, an output node and an input node of the first inverter circuit being coupled to an input node and an output node of the second inverter circuit, respectively, and a control circuit configured to, after powering off one or more first memory cells that are not required to retain data among the memory cells, put the bistable circuits in remaining one or more second memory cells of the memory cells into the second mode, and supply a second power supply voltage, at which the bistable circuit in the second mode can retain data, to the bistable circuits in the one or more second memory cells while maintaining the second mode, the second power supply voltage being lower than a first power supply voltage that is supplied to the bistable circuit when data is read and/or written.

    CIRCUIT MÉMOIRE ADAPTÉ À METTRE EN OEUVRE DES OPÉRATIONS DE CALCUL
    6.
    发明公开
    CIRCUIT MÉMOIRE ADAPTÉ À METTRE EN OEUVRE DES OPÉRATIONS DE CALCUL 审中-公开

    公开(公告)号：EP3660849A1

    公开(公告)日：2020-06-03

    申请号：EP19209000.9

    申请日：2019-11-13

    申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives

    发明人： CHARLES, Henri-Pierre ,  KOOLI, Maha ,  NOEL, Jean-Philippe

    IPC分类号： G11C7/10 ,  G11C11/417

    摘要： La présente description concerne un circuit mémoire (200) comportant :
    - une pluralité de cellules élémentaires de stockage (10) agencées en matrice selon des rangées et des colonnes, les cellules d'une même colonne partageant une même ligne de bit de lecture (RBL) et une même ligne de bit d'écriture (WBL) ;
    - un circuit interne de contrôle (CTRL) adapté à mettre en oeuvre une opération de calcul comprenant l'activation simultanée en lecture d'au moins deux rangées de la matrice ; et
    - un circuit de permutation (30) comportant un registre d'entrée de données (32), un registre de configuration (36), et un port de sortie (34), le circuit de permutation (30) étant adapté à fournir sur son port de sortie (34) les données mémorisées dans son registre d'entrée (32) permutées selon une permutation définie en fonction de l'état de son registre de configuration (36) .

    SYSTEM AND METHOD TO REGULATE OPERATING VOLTAGE OF A MEMORY ARRAY
    8.
    发明公开
    SYSTEM AND METHOD TO REGULATE OPERATING VOLTAGE OF A MEMORY ARRAY 有权
    系统在维也纳ZUR REGULIERUNG DER BETRIEBSSPANNUNG EINER SPEICHERMATRIX

    公开(公告)号：EP2973577A2

    公开(公告)日：2016-01-20

    申请号：EP14722821.7

    申请日：2014-03-11

    申请人： Qualcomm Incorporated

    发明人： SONG, Stanley Seungchul ,  WANG, Zhongze

    IPC分类号： G11C11/417 ,  G11C11/413 ,  G11C5/14 ,  G11C7/04

    CPC分类号： G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

    摘要： A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

    摘要翻译： 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。

    MEMORY CONTROL CIRCUIT AND MEMORY CIRCUIT
    9.
    发明公开
    MEMORY CONTROL CIRCUIT AND MEMORY CIRCUIT 审中-公开
    SPEICHERSTEUERUNGSSCHALTUNG UND SPEICHERSCHALTUNG

    公开(公告)号：EP2605247A1

    公开(公告)日：2013-06-19

    申请号：EP10855903.0

    申请日：2010-08-13

    申请人： Fujitsu Limited

    发明人： IJITSU, Kenji

    IPC分类号： G11C11/417 ,  G11C11/41

    CPC分类号： G11C7/00 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/18 ,  G11C11/419

    摘要： A memory circuit includes a plurality of divided memory cell blocks, a write circuit and a read circuit which connect via a pair of bit lines to each of the divided memory cell blocks. The output of write data to one of the bit line of the write circuit is made to be performed by one system. It is possible to achieve an increase of speed by bit lien division while reducing increase in the memory circuit area accompanying the bit line division.

    摘要翻译： 存储器电路包括多个划分的存储单元块，写入电路和读取电路，其经由一对位线连接到每个划分的存储单元块。 写入数据到写入电路的位线之一的输出由一个系统执行。 可以通过比特划分来实现速度的提高，同时减少伴随位线划分的存储器电路区域的增加。

    SRAM LEAKAGE REDUCTION CIRCUIT
    10.
    发明授权
    SRAM LEAKAGE REDUCTION CIRCUIT 有权
    SRAM漏电流降低电路

    公开(公告)号：EP2022056B1

    公开(公告)日：2011-11-23

    申请号：EP07761457.6

    申请日：2007-04-27

    申请人： Mosaid Technologies Incorporated

    发明人： ZAMPAGLIONE, Michael, Anthony ,  TOOHER, Michael

    IPC分类号： G11C5/14 ,  G11C11/417

    CPC分类号： G11C5/147 ,  G11C11/417 ,  H03K19/0008

    摘要： A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD-(1.5*Vth), or maintain 1.5*Vth across the memory cells, where Vth is a threshold voltage of an SRAM memory cell transistor and VDD is a positive supply voltage. By tracking the Vth of the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.