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1241 条记录 (耗时 0.021 秒)

    RECEIVER CIRCUIT, CORRESPONDING SYSTEM AND METHOD
    2.
    发明公开
    RECEIVER CIRCUIT, CORRESPONDING SYSTEM AND METHOD 审中-公开

    公开(公告)号：EP4401323A1

    公开(公告)日：2024-07-17

    申请号：EP23219526.3

    申请日：2023-12-21

    申请人： STMicroelectronics International N.V.

    发明人： SPINA, Nunzio ,  CASTORINA, Alessandro ,  PALMISANO, Giuseppe

    IPC分类号： H04B1/16 ,  H04B1/30 ,  H04L27/02 ,  H03M1/06

    CPC分类号： H04B1/16 ,  H04B1/30 ,  H04L27/02 ,  H03M1/0607

    摘要： A receiver circuit for use, for instance, in interchip data communication in the automotive sector comprises an envelope detector (M1, M2, RL1, CED) configured to receive (RX1) an on-off keying, OOK signal modulated over a RF carrier. A differential stage (121, 122, RL2) has a first input (VA) coupled to the envelope detector (M1, M2, RL1, CED) and a second input (VB) configured to receive a reference signal. A comparator (16) is coupled (14) to first (C) and second (D) output nodes of the differential stage (121, 122, RL2) produces a PWM-modulated signal (PWMOUT) having on and off times. Offset compensation circuitry comprises a first switch (S1,Φ1) to short-circuit the input to the envelope detector (M1, M2, RL1, CED), a storage capacitor (CH) coupled to the second input (VB) of the differential stage (121, 122, RL2) and a second switch (S1,Φ2) to feed back to the storage capacitor (CH) a signal (18) indicative of the difference between the first (C) and the second (D) output nodes of the differential stage (121, 122, RL2), and a third switch (S3,Φ1) to short-circuit the input to the comparator (16) . Logic circuitry (100) activates the offset compensation circuitry in a sequence of phases comprising a start-up phase (SUP) and at least one standby phase (STBY) wherein the first (S1,Φ1), second (S2,Φ2) and third (S3,Φ1) switches are made conductive in the absence of the PWM-modulated signal (PWMOUT), and a working phase (WP) alternating with the start-up phase (SUP) or the at least one standby phase (STBY) in the presence of the PWM-modulated signal (PWMOUT) wherein the first (S1,Φ1), second (S2,Φ2) and third (S3,Φ1) switches are made conductive during off times (T2) of the PWM-modulated signal (PWMOUT).

    HIGH-BANDWIDTH VIBRATION SENSOR
    3.
    发明公开
    HIGH-BANDWIDTH VIBRATION SENSOR 审中-公开

    公开(公告)号：EP4400816A1

    公开(公告)日：2024-07-17

    申请号：EP23151597.4

    申请日：2023-01-13

    申请人： Sensirion AG

    发明人： Looser, Flurin ,  Mrcarica, Zeljko ,  Ryter, Roland ,  Schalch, Thomas ,  Keitel, Robert Christian

    IPC分类号： G01H1/00 ,  G01H3/00 ,  H03M1/06 ,  H03M1/12 ,  G01H11/06 ,  G01M13/028 ,  H03H11/12

    CPC分类号： G01H1/00 ,  G01H3/00 ,  H03M1/0626 ,  H03M1/12 ,  G01H11/06 ,  G01M13/028 ,  H03H11/1217 ,  G01M15/00 ,  G01M5/0066

    摘要： The invention refers to a sensor arrangement (100) for sensing vibrations. The sensor arrangement (100) comprises a vibration sensor (10) configured to provide a sensor signal (101 and an amplifier unit (20) configured to amplify the sensor signal (101) over a predefined operation frequency band (61, 71) with a gain according to a first transfer function (60, 70) and to provide an analog amplifier output signal (102. The sensor arrangement further comprises an analog-to-digital converter, ADC, (30) configured to convert the amplifier output signal (102) into a first digital signal (103); and a digital compensation unit (40) configured to apply a second transfer function on the first digital signal (103), wherein the second transfer function is an inverse function of the first transfer function (60, 70). The operation frequency band (61, 71) comprises a low-frequency band (62, 72) and a high-frequency band (63, 73) and the gain of the predefined first transfer function (60, 70) is lower in the low-frequency band (62, 72) than in the high-frequency band (63, 73).

    SAMPLING CIRCUITRY
    6.
    发明公开
    SAMPLING CIRCUITRY 审中-公开

    公开(公告)号：EP4336506A1

    公开(公告)日：2024-03-13

    申请号：EP23192952.2

    申请日：2023-08-23

    申请人： Socionext Inc.

    发明人： SANTHOSH KUMAR, Sandeep ,  CRETU, Vlad ,  KUDO, Masahiro

    IPC分类号： G11C27/02 ,  H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

    摘要： A sample and hold circuit comprising: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.