公开(公告)号：JP2008159818A

公开(公告)日：2008-07-10

申请号：JP2006346817

申请日：2006-12-22

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： NAGASE KENJI ,  KAWABATA KENICHI

IPC: H05K1/11 ,  H01L23/12 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure or the like capable of surely connecting a body to be wired and a wiring layer while maintaining an insulation between the wiring layer and an adjacent wiring layer and capable of achieving a high-density mounting by narrowing pitches. SOLUTION: In a semiconductor built-in board 1, conductor patterns 13 are formed on both surfaces of a core board 11, and a semiconductor device 14 is arranged in a resin layer 16 laminated on the core board 11. Via holes 19a and 19b are formed to the resin layer 16 so that the conductor patterns 13 and bumps 14p for the semiconductor device 14 are projected from the resin layer 16. The bumps 14p and the conductor patterns 13 are connected to via-hole electrode sections 23a and 23b having sectional areas increasing towards the bottom sections of the via holes 19a and 19b in the via holes 19a and 19b. Air gaps are defined between the via-hole electrode sections 23a and 23b and the upper sections of the inner walls of the via holes 19a and 19b. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：为了提供一种能够在保持布线层和相邻布线层之间的绝缘的同时可靠地连接待布线体和布线层的布线结构等，并且能够实现高密度 通过缩小间距安装。 解决方案：在半导体内置板1中，在芯板11的两个表面上形成导体图案13，并且将半导体器件14布置在层压在芯板11上的树脂层16中。通孔19a 和19b形成在树脂层16上，使得用于半导体器件14的导体图案13和凸起14p从树脂层16突出。凸块14p和导体图案13连接到通孔电极部分23a和23b 具有朝向通孔19a和19b中的通孔19a和19b的底部部分的截面积增加。 通孔电极部23a，23b与通路孔19a，19b的内壁的上部分别形成有气隙。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003197835A

公开(公告)日：2003-07-11

申请号：JP2001395458

申请日：2001-12-26

Applicant: TDK CORP

Inventor： TAKATANI MINORU ,  TAKAHARA MASASHI ,  NAGASE KENJI

IPC: H05K7/20 ,  H01L23/12 ,  H01L23/36 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To provide a power amplification module and a substrate therefor in which a heat dissipation is excellent, it is effective to prevent a reduction in an output or a reduction in efficiency due to an increase in an on-resistance, a mounting assembly is easy, and a mechanical strength is excellent. SOLUTION: A substrate 1 has a hole 7 in a plane and a plated film 75 is adhered to an internal plate 72 of the hole 7. A thermal conduction block 5 is combined with the hole 7 of the substrate 1 and joined to the plated film 75 of the internal plate 72 of the hole 7. A semiconductor chip 3 is mounted on a surface of the thermal conduction block 5. COPYRIGHT: (C)2003,JPO