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公开(公告)号：JP2013058777A
公开(公告)日：2013-03-28
申请号：JP2012244519
申请日：2012-11-06
Inventor： NAGASE KENJI , UEMATSU HIROYUKI , KAWABATA KENICHI
Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board which is capable of suppressing a plating failure in a connection hole such as a via formed in the printed wiring board and thus allows connection reliability to be improved, and a method for manufacturing the same.SOLUTION: A printed wiring board 100 includes: a thermosetting resin sheet 16 (insulating layer) comprising a via hole 20 (through hole) constituted of inner wall parts having different taper angles; a copper foil 17 (conductor layer) provided on the thermosetting resin sheet 16; and a wiring pattern 13 (wiring layer) which is provided so as to be exposed from the via hole 20 and is electrically connected to the copper foil 17 via the via hole 20.
Abstract translation: 要解决的问题：提供一种能够抑制在印刷线路板中形成的通孔等连接孔中的电镀故障的印刷电路板，能够提高连接可靠性，制造方法 一样。 解决方案：印刷电路板100包括：热固性树脂片16（绝缘层），其包括由具有不同锥角的内壁部分构成的通孔20（通孔） 设置在热固性树脂片16上的铜箔17（导体层） 以及布线图案13（布线层），其被设置为从通孔20露出并经由通孔20与铜箔17电连接。版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2008218522A
公开(公告)日：2008-09-18
申请号：JP2007050490
申请日：2007-02-28
Inventor： NAGASE KENJI , KAWABATA KENICHI
CPC classification number: H01L24/82 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L2224/24051 , H01L2224/24226 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H05K1/185 , H05K3/064 , H05K3/4007 , H05K3/421 , H05K3/4652 , H05K2201/0367 , H05K2201/09472 , H05K2201/09645 , H05K2201/09745 , H05K2203/054 , H05K2203/1152 , Y10T29/49155 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure or the like for sufficiently improving connection capability between an object to be connected and a wiring pattern (layer) connected to the connection object. SOLUTION: In a circuit board 1 including a built-in semiconductor, a conductor pattern 13 is formed in both surfaces of a core board 11 and a semiconductor device 14 is arranged within a resin layer 16 laminated on the core board 11. The conductor pattern 13 and a bump 14p of the semiconductor device 14 are provided on the resin layer 16 and via-holes 19a, 19b are formed on the upper part of these elements. Moreover, within the internal side of the via-holes 19a, 19b, via-hole electrodes 23a, 23b are connected to the conductor pattern 13 and the bump 14p of the semiconductor device 14. The via-hole electrodes 23a, 23b include recesses on the upper surface thereof and are provided in such a manner that side walls including edge end portions of the recesses are provided not in contact with the internal walls of the via-holes 19a, 19b. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：提供一种用于充分提高要连接的对象与连接到连接对象的布线图案（层）之间的连接能力的布线结构等。 解决方案：在包括内置半导体的电路板1中，在芯板11的两个表面上形成导体图案13，并且将半导体器件14布置在层压在芯板11上的树脂层16内。 半导体器件14的导体图案13和凸块14p设置在树脂层16上，并且在这些元件的上部形成有通孔19a，19b。 此外，在通孔19a，19b的内侧，通孔电极23a，23b连接到导体图案13和半导体器件14的凸块14p。通孔电极23a，23b包括凹槽 其上表面设置成使得包括凹部的边缘端部的侧壁不与通孔19a，19b的内壁接触。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2007173276A
公开(公告)日：2007-07-05
申请号：JP2005364458
申请日：2005-12-19
Inventor： NAGASE KENJI , KAWABATA KENICHI
CPC classification number: H01L25/16 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/24226 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01078 , H01L2924/14 , H01L2924/30107 , H05K1/185 , H05K3/0044 , H05K3/4652 , H05K2201/0209 , H05K2201/09509 , H05K2201/09518 , H05K2201/10674 , H05K2203/025 , H05K2203/0554 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49139 , Y10T29/49151 , Y10T29/49155
Abstract: PROBLEM TO BE SOLVED: To cope with an increase in the number of pad electrodes or fine pitch without damaging semiconductor IC chips built in a resin layer by heat or application of load (stress). SOLUTION: First, copper foils 12 provided on both surfaces of a core substrate 11 are selectively removed by photolithography and etching, thus forming a conductive pattern 13 such as wiring or land, on the core substrate 11. Next, a semiconductor IC chip 14 is mounted face-up in a specified area on the core substrate 11, and then it is buried in a resin sheet 16. A copper foil 17 formed on the surface of the resin sheet 16 is selectively removed by conformal treatment, thus forming a mask pattern for forming a via hole. Then, the copper foil 17 applied with the conformal treatment is used as a mask, and sand-blasting is conducted to form a via hole 19. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：为了防止焊盘电极的数量的增加或微细间距，而不会损坏通过加热或施加负载（应力）而在树脂层中内置的半导体IC芯片。 解决方案：首先，通过光刻和蚀刻选择性地去除设置在芯基板11的两个表面上的铜箔12，从而在芯基板11上形成诸如布线或焊盘的导电图案13。 芯片14面朝上安装在芯基板11上的特定区域中，然后被埋在树脂片16中。通过保形处理选择性地去除形成在树脂片16表面上的铜箔17，从而形成 用于形成通孔的掩模图案。 然后，使用施加了保形处理的铜箔17作为掩模，进行喷砂以形成通孔19.（C）2007，JPO＆INPIT
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公开(公告)号：JP2010232418A
公开(公告)日：2010-10-14
申请号：JP2009078223
申请日：2009-03-27
Inventor： UEMATSU HIROYUKI , KAWABATA KENICHI , NAGASE KENJI
IPC: H05K3/46
CPC classification number: H05K3/427 , H05K3/002 , H05K3/0035 , H05K3/0038 , H05K3/0041 , H05K3/0044 , H05K3/061 , H05K3/064 , H05K3/382 , H05K3/389 , H05K3/421 , H05K3/4652 , H05K2201/0347 , H05K2201/0355 , H05K2201/0358 , H05K2201/0394 , H05K2203/025 , H05K2203/0353 , H05K2203/054 , H05K2203/0585 , H05K2203/0733
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring board capable of readily forming a thin-film pattern which is superior in uniformity as a mask for forming a wiring layer, even if there are multilayer wiring board warpages or irregularities.
SOLUTION: A primer-coated metal foil 20 constituted of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, with metal layers 12 and 13 prepared on a support base 11, and the primer-coated metal foil and the double-face CCL are bonded and then the primer resin layer 21 is cured. A via Vb is, thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed thereon. After that, the etched down metal-plated layer 30 and the metal layer 22 are patterned; and by using the patterned layers as a mask, the primer resin layer 21 is patterned. By using the patterned primer resin layer 21 as a mask, the metal layer 12 of the double-face CCL 10 and the metal-plated layer 30 are patterned, and a wiring pattern is formed.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 解决的问题：为了提供一种制造能够容易地形成均匀性优异的薄膜图案的多层布线板的方法，作为用于形成布线层的掩模，即使存在多层布线板翘曲或 违规行为。 解决方案：将由底漆树脂层21和金属层22构成的底漆涂覆的金属箔20放置在双面CCL 10的表面上，在支撑基底11上制备金属层12和13， 并且底漆涂覆的金属箔和双面CCL结合，然后底漆树脂层21固化。 之后，从金属层22侧形成通孔Vb，在其上形成金属板层30。 之后，对蚀刻的金属镀层30和金属层22进行图案化; 并且通过使用图案层作为掩模，对底漆树脂层21进行图案化。 通过使用图案化底漆树脂层21作为掩模，对双面CCL 10的金属层12和金属镀层30进行图案化，形成布线图案。 版权所有（C）2011，JPO＆INPIT
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5.发明专利
公开(公告)号：JP2009111416A
公开(公告)日：2009-05-21
申请号：JP2009003930
申请日：2009-01-09
Inventor： NAGASE KENJI , KAWABATA KENICHI
Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure in which insulation between adjacent wiring layers is maintained while a body to be wired is surely connected to a wiring layer to achieve high-density mounting through a reduction in mounting pitches.
SOLUTION: A semiconductor-incorporating board 1 is made by forming conductive patterns 13 respectively on both surfaces of a core substrate 11 and disposing a semiconductor device 14 in a resin layer 16 overlaid on the core substrate 11. Via-holes 19a and 19b are formed on the resin layer 16, so that the conductive pattern 13 and a bump 14p of the semiconductor device 14 project out of the resin layer 16. Inside the via-holes 19a and 19b, the bump 14p and the conductive pattern 13 are connected to via-hole electrodes 23a and 23b whose sectional areas are enlarged toward the bottom of the via-holes 19a and 19b, respectively. Gaps are formed between the via-hole electrodes 23a and 23b and the inner wall upper portions of the via-holes 19a and 19b, respectively.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供一种布线结构，其中当布线体被确定地连接到布线层时，相邻布线层之间的绝缘被保持，从而通过降低安装间距来实现高密度安装。 解决方案：通过在芯基板11的两个表面上分别形成导电图案13并将半导体器件14设置在覆盖在芯基板11上的树脂层16中来形成半导体集成板1。通孔19a和 19b形成在树脂层16上，使得导电图案13和半导体器件14的凸块14p从树脂层16突出。在通孔19a和19b的内部，凸块14p和导电图案13是 连接到截面积分别朝向通孔19a和19b的底部扩大的通孔电极23a和23b。 通孔电极23a，23b与通路孔19a，19b的内壁上部分别形成有间隙。 版权所有（C）2009，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2005039263A
公开(公告)日：2005-02-10
申请号：JP2004194497
申请日：2004-06-30
Inventor： TAKAHARA MASASHI , NAGASE KENJI
Abstract: PROBLEM TO BE SOLVED: To provide a multiplayer substrate for a circuit module, for which the physical size can be made small and electric power supply efficiency can be improved. SOLUTION: The multiplayer substrate 7 for a circuit module, having a dc bias circuit 216, is composed of laminated multiple functional layers 71-77. The dc bias circuit 216 includes a parallel circuit 218 of an inductor L5 and a capacitor C10, and comprises the bias circuit of an active element 212 included in the circuit module. A conductive pattern comprising the inductor L5 is arranged for the functional layer 75 facing a conductive pattern GND3 on both sides of an insulating layer 752. For the thickness t1 of the conductive pattern comprising the inductor L5 and the thickness t2 of the insulator 752, t1>t2 is satisfied. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 解决的问题：为了提供可以使物理尺寸变小的电路模块的多玩家基板，并且可以提高电力供应效率。 解决方案：具有直流偏置电路216的电路模块用多层基板7由层叠的多功能层71-77构成。 直流偏置电路216包括电感器L5和电容器C10的并联电路218，并且包括电路模块中包括的有源元件212的偏置电路。 布置包括电感器L5的导电图案，用于面向绝缘层752两侧的导电图案GND3的功能层75.对于包括电感器L5的导电图案和绝缘体752的厚度t2的厚度t1，t1 > t2满足。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2009200356A
公开(公告)日：2009-09-03
申请号：JP2008042062
申请日：2008-02-22
Inventor： NAGASE KENJI , UEMATSU HIROYUKI , KAWABATA KENICHI
CPC classification number: H05K3/0035 , H05K1/115 , H05K3/0055 , H05K3/381 , H05K2201/09509 , H05K2201/09827 , H05K2203/025 , H05K2203/0554 , H05K2203/0557 , Y10T29/49155 , Y10T29/49165
Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board and a manufacturing method therefor, which can prevent a plating failure in a connection hole such as a via to be formed in the printed wiring board, thereby can enhance the connection reliability. SOLUTION: The printed wiring board 100 includes a thermosetting resin sheet 16 (insulation layer) having a via hole 20 (through hole) configured with an inner wall whose taper angle varies depending on its part, a copper foil 17 (conductor layer) provided on the thermosetting resin sheet 16, and a wiring pattern 13 (wiring layer) which is provided so as to be exposed from the via hole 20 and is electrically connected with the copper foil 17 through the via hole 20. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：为了提供一种可以防止在印刷电路板中形成的通孔等连接孔中的电镀故障的印刷布线板及其制造方法，从而可以提高连接可靠性。 解决方案：印刷电路板100包括具有通孔20（通孔）的热固性树脂片16（绝缘层），该通孔20（通孔）由锥形角度根据其部分而变化的内壁构成，铜箔17（导体层 ）和布置图案13（布线层），布线图案13（布线层）设置成从通孔20露出，并通过通孔20与铜箔17电连接。 （C）2009，JPO＆INPIT
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公开(公告)号：JP2007021362A
公开(公告)日：2007-02-01
申请号：JP2005207093
申请日：2005-07-15
Inventor： GOTO MASASHI , KUWAJIMA HAJIME , NAGASE KENJI
IPC: B08B3/12
Abstract: PROBLEM TO BE SOLVED: To provide an ultrasonic treatment apparatus which can surely carry out an ultrasonic treatment of a material to be treated by uniforming sound pressure distribution in a treatment liquid using a simple constitution.
SOLUTION: The ultrasonic treatment apparatus has a treatment tank for storing the treatment liquid and also immersing the material to be treated into the treatment liquid, a vibration generating member which is installed on the bottom side of the treatment tank and generates an ultrasonic vibration, and a vibration transmitting member which contacts with the vibration generating member and affects the ultrasonic vibration from the vibration generating member to the treatment liquid, wherein a plurality of convex spherical surfaces are arranged on the surface of the vibration transmitting member.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 解决的问题：提供一种超声波处理装置，其能够通过使用简单的结构在处理液中均匀化声压分布，可靠地对被处理材料进行超声波处理。 解决方案：超声波处理装置具有用于储存处理液并且还将待处理材料浸入处理液中的处理槽，安装在处理槽底部并产生超声波的振动产生部件 振动，以及与振动发生部件接触并影响从振动产生部件到处理液体的超声波振动的振动传递部件，其中在振动传递部件的表面上布置有多个凸形球面。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2004014807A
公开(公告)日：2004-01-15
申请号：JP2002166295
申请日：2002-06-06
Inventor： TAKAHARA MASASHI , NAGASE KENJI
CPC classification number: H01L2224/48091 , H01L2224/48227 , H01L2224/48479 , H01L2924/00014 , H01L2924/1305 , H01L2924/00 , H01L2224/4554
Abstract: PROBLEM TO BE SOLVED: To provide a power amplifier module which can reduce the plane area of a substrate and is superior in the heat dissipation property. SOLUTION: A substrate 7 has a recess part 41 having a bottom on a mounting plane 702. A heat conductive film 43 is attached to a base 411 and inner wall planes 412, 413 of the recess part 41. A semiconductor chip 20 is disposed inside the recess part 41, and is thermally connected to the heat conductive film 43 on the base 411. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2010073809A
公开(公告)日：2010-04-02
申请号：JP2008238268
申请日：2008-09-17
Inventor： NAGASE KENJI , UEMATSU HIROYUKI , KAWABATA KENICHI
IPC: H05K3/40
CPC classification number: H05K3/427 , H05K3/025 , H05K3/4007 , H05K3/421 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0554
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a printed circuit board that can simply and certainly form a minute wiring pattern with a thin layer by simplifying the process to improve the productivity when forming a wiring structure with a filled via. SOLUTION: The method of manufacturing a printed circuit board covers a resinous substrate 11 (insulating body) with a carrier foil attached metal foil 20 having a carrier-foil layer 22 and a metal-foil layer 21 such that the metal-foil layer 21 comes into contact with one surface of the resinous substrate 11; after that, a via-hole V (connection hole) is formed, via filling is done, and a plated film 32 is formed; and then, the carrier-foil layer 22 of the carrier foil attached metal foil 20 is peeled off from the metal-foil layer 21. Then, the metal-foil layer 21 remaining attached on the resinous substrate 11 is patterned, thus forming a wiring pattern 23. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种制造印刷电路板的方法，该印刷电路板可以简单且肯定地形成具有薄层的微小布线图案，通过简化在用填充的通孔形成布线结构时提高生产率的工艺。 解决方案：制造印刷电路板的方法覆盖树脂基板11（绝缘体），其具有带载体箔的金属箔20，金属箔20具有载体箔层22和金属箔层21，使得金属箔 层21与树脂基板11的一个表面接触; 之后，形成通孔V（连接孔），通过填充，形成镀膜32。 然后将载体箔附着金属箔20的载体箔层22从金属箔层21剥离。然后，将残留在树脂基板11上的金属箔层21图案化，从而形成布线 模式23.版权所有（C）2010，JPO＆INPIT
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