公开(公告)号：JPS6018141B2

公开(公告)日：1985-05-09

申请号：JP9910073

申请日：1973-09-03

Applicant: NIPPON ELECTRIC CO

Inventor： HARUYAMA TAKAICHI ,  NAKAZAWA SHUJI

IPC: H01C13/02 ,  H01C1/16 ,  H01L21/331 ,  H01L21/70 ,  H01L21/822 ,  H01L27/01 ,  H01L27/04 ,  H01L29/02 ,  H01L29/66 ,  H01L29/73

公开(公告)号：JPS6074463A

公开(公告)日：1985-04-26

申请号：JP18214683

申请日：1983-09-29

Applicant: FUJITSU LTD

Inventor： HAYASHI MASAAKI

IPC: H01C17/242 ,  H01L21/70 ,  H01L27/01

Abstract: PURPOSE:To prevent the damage of the conductive pattern located under a resistance film by a method wherein a protective film, consisting of material which reflects or shuts off a laser beam or hardly fused by the laser beam, is formed in advance under the resistance film to be trimmed. CONSTITUTION:A conductive pattern C1, an insulating layer I1, a conductive pattern C2, an insulating layer I2 and a conductive pattern C3 are laminated in the above-mentioned order on the substrate 15 consisting of an insulating material, and between each layer is connected by a wire 16. A resistance film 1 is provided on the top layer, and a protective layer 7 which reflects or shuts off layer beam or hardly fused by the laser beam is formed in advance. After the above- mentioned layers and film have been sintered, a trimming work is performed on the resistance film 1.

公开(公告)号：JPS6032357A

公开(公告)日：1985-02-19

申请号：JP14318083

申请日：1983-08-03

Applicant: SHARP KK

Inventor： SAKIYAMA KEIZOU ,  NAKANO AKIHIKO ,  OKAYAMA MORIYA

IPC: H01L21/70 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

Abstract: PURPOSE:To obtain an integrated circuit which is improved for the reliability at the operating time by using a substrate structure ready in its manufacture by forming the substrate for associating an N-channel MOSFET by altering the surface of an N type silicon substrate to P type. CONSTITUTION:An N type silicon layer 2 is formed on one surface of an N type silicon substrate 1, and a P type region 3 is then formed on the surface of the silicon layer 2. The region 3 is formed by inverting the conductive type over part or the entire surface of the layer 2. The layer 2 is formed by epitaxial growing, and the region 3 is formed by introducing P type impurity to the surface layer by thermal diffusing. The N type impurity is introduced into the region 3 to form source and drain region, and a gate insulating film and a gate electrode are then, formed, thereby forming a D-RAM made of N-MOSFET.

公开(公告)号：JPS6031232A

公开(公告)日：1985-02-18

申请号：JP13885883

申请日：1983-07-29

Applicant: TOSHIBA KK

Inventor： SAMATA SHIYUUICHI ,  MATSUSHITA YOSHIAKI

IPC: H01L21/70 ,  H01L21/322 ,  H01L21/324 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/167

Abstract: PURPOSE:To form a substrate which has characteristics of both an IG wafer and an epitaxial wafer by forming a high resistance single crystal semiconductor thin layer on a low resistance semiconductor substrate, implanting electrically inert impurity ions, and forming a high resistance single crystal semiconductor thin layer thereon. CONSTITUTION:A P type single crystal silicon thin layer 12 having approx. 1cm of specific resistance and approx. 3mum of thickness is formed on the main surface of a boron-doped P type silicon substrate 11 having approx. 0.01OMEGAcm of specific resistance, oxygen ions are implanted to the layer 12 to form many defects 13. Then, epitaxial grown is performed in an atmosphere of SiC4+H2, a P type single crystal silicon thin layer 14 having approx. 1cm of specific resistance is formed on the surface of the layer 12, it is heat treated in an oxygen atmosphere of approx. 700 deg.C. Thus, a semiconductor substrate which has excellent characteristics of both an intrinsic gettering wafer and an epitaxial wafer can be formed.

公开(公告)号：JPS6015963A

公开(公告)日：1985-01-26

申请号：JP12301483

申请日：1983-07-06

Applicant: TOSHIBA KK

Inventor： OOTSUKA HIDEO ,  IWAI HIROSHI

IPC: H01L21/70 ,  H01L21/8242 ,  H01L27/10 ,  H01L21/72

Abstract: PURPOSE:To obtain an MOS type integrated circuit of high degree of integration, in which the malfunction of a memory cell, etc. due to a small number of unnecessary carriers from an SSB circuit is prevented, by using an Si substrate, the inside thereof has a minute defective region and in a non-defective region thereof an isolation material reaching to the minute defective region is fitted, and forming the SSB circuit in the non-defective region isolated by the isolation material. CONSTITUTION:A silicon substrate 1, to a surface layer thereof non-defective regions 3, 3' are formed and to the inside thereof a minute defective region 4 is shaped, is prepared, a resist pattern 7, to which isolation region prearranged actions are bored, is formed on an oxide film 2 on the main surface of the substrate 1, the oxide film 2 is removed while using the pattern 7 as a mask, and the exposed substrate 1 is etched selectively to shape groove sections 8, bottoms thereof reach to the minute defective region 4. The pattern 7 is removed, the groove sections 8 are oxidized through thermal oxidation in wet oxygen, and oxide films 2, 2' are further removed and isolation materials 9 are buried in the substrate 1. An SSB circuit is formed in a region 10 in the non-defective region 3 isolated by the isolation materials 9 and a memory cell for a dynamic RAM in a region 11 respectively.

公开(公告)号：JPS59225556A

公开(公告)日：1984-12-18

申请号：JP10106483

申请日：1983-06-07

Applicant: FUJITSU LTD

Inventor： MIYAJIMA EIJI

IPC: H01C17/22 ,  H01L21/60 ,  H01L21/70 ,  H01L27/01 ,  H05K1/16 ,  H05K3/24 ,  H01L23/48

Abstract: PURPOSE:To contrive to enhance certainty of bonding, and to enhance precision of a formed resistance element at manufacture of a hybrid integrated circuit by a method wherein after the pattern of a base layer for a bonding pad consisting of an Au thin film is formed on a substrate, annealing treatment is performed, and then an Au layer is formed according to plating. CONSTITUTION:An Au layer 3 is evaporated on an Ni-Cr layer 2 adhered on a glazed alumina substrate 1. Annealing is performed to stabilize the resistance element formed in such a way. The annealing (b) thereof is executed in condition such as for 4hr at 275 deg.C to insure the desired strength at the later process of a hybrid integrated circuit, for example. The after a plated Au layer 4 is formed (c) on the pad part, trimming (d) of the resistance element is performed, and after then loading (e) of individual elements, outside lead terminals, etc. and connection of the circuits of the loaded elements are performed. Because diffusion of the Ni-Cr layer 2 to the plated Au layer 4 of the bonding pad is not generated in the hybrid integrated circuit manufactured in such a way, bonding to the pad can be performed surely, and the constant of the formed resistance element is not changed according to bonding.

公开(公告)号：JPS59225555A

公开(公告)日：1984-12-18

申请号：JP9937583

申请日：1983-06-06

Applicant: HITACHI LTD

Inventor： KOSEKI MAMORU

IPC: H01C17/242 ,  H01L21/70 ,  H01L27/01 ,  H01C17/22

Abstract: PURPOSE:To contrive to curtail operating hours at manufacturing time of a hybrid IC by a method wherein recording of a lot, etc. is performed in the same process with laser trimming, and moreover symbolized short lines are carved according to laser. CONSTITUTION:Trimming according to laser of a resistor 2 on a ceramic substrate 1 and trimming of the stamp of a symbolized lot number 3' are performed in the same process. Because the stamp formed according to laser is hard to recognize when it is on the substrate, resistor paste 4 is used for lot recording, the stamp is printed at the same time with the resistor, and when marking is performed thereon according to laser in the same condition with the resistor trimming, the lot number becomes easily to recognize. Moreover recording of the lot is made to possible to perform in the same process with the laser trimming, and high speed lot recording can be attained.

公开(公告)号：JPS59207234A

公开(公告)日：1984-11-24

申请号：JP7480284

申请日：1984-04-13

Applicant: Porionitsukusu Corp

Inventor： MAAUIN EFU FUUBAA ,  AN BII SARAMON ,  JIYAN BANDEBURUTO

IPC: H05K1/03 ,  B32B15/08 ,  H01L21/70 ,  H05K1/16 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/182 ,  H01L21/702 ,  H05K1/162 ,  H05K1/165 ,  H05K3/381 ,  H05K3/4661 ,  H05K2201/09563 ,  H05K2201/09909

公开(公告)号：JPS59182559A

公开(公告)日：1984-10-17

申请号：JP5508283

申请日：1983-04-01

Applicant: Hitachi Ltd

Inventor： NOJIRI KAZUO ,  ITOU KATSUHIKO ,  AOSHIMA TAKAAKI

IPC: H01L27/00 ,  H01L21/322 ,  H01L21/70 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10805

Abstract: PURPOSE:To obtain a semiconductor device of excellent reliability and stability by making a crystal defect reducing generation-recombination center contain in a semiconductor region of a conduction type different from a semiconductor substrate when the region is formed to the semiconductor substrate and the semiconductor device having a memory function is manufactured. CONSTITUTION:A thick field insulating film 2 is formed to the peripheral section of a semiconductor substrate 1 while using a p type channel stopper region 3 as an underlay, and the surface of the substrate 1 surrounded by the film 2 is coated with a thin insulating film 4 for shaping capacitance and a gate. An n type source or drain region and a region 7 connected to a bit wire 10 are formed to the substrate 1 through ion implantation, etc. A capacitance electrode 5 and a gate electrode 6 are formed on both sides of the source-drain region 7 while holding the region 7, and coated with a PSG film 8. In the constitution, crystal defects of approximately 1X10 number/cm or more in an extent that leakage currents are not generated in a p-n junction are made contain in the source-drain region 7 through heat treatment.

Abstract translation: 目的：为了获得具有优异可靠性和稳定性的半导体器件，当半导体衬底形成区域时，通过使晶体缺陷减少生成复合中心包含在与半导体衬底不同的导电类型的半导体区域中，并且半导体器件具有 制作记忆功能。 构成：在使用ap +型沟道阻挡区域3作为衬底的同时，在半导体衬底1的周边部分形成厚场绝缘膜2，并且由膜2包围的衬底1的表面涂覆有 用于成形电容的薄绝缘膜4和栅极。 通过离子注入等将n +型源极或漏极区域和连接到位线10的区域7形成在基板1上。电容电极5和栅电极6形成在源极 - 漏极区域7，同时保持区域7，并涂覆有PSG膜8.在该结构中，在pn结中不产生漏电流的程度的约1×10 2 / cm 2或更大的晶体缺陷 通过热处理在源极 - 漏极区域7中制成。

公开(公告)号：JPS5942461B2

公开(公告)日：1984-10-15

申请号：JP8457681

申请日：1981-06-01

Applicant: Sanyo Denki Kk ,  Tokyo Sanyo Denki Kk

Inventor： KAZAMI AKIRA

IPC: H01C17/06 ,  H01C17/24 ,  H01C17/242 ,  H01L21/70 ,  H01L27/01 ,  H05K1/16

CPC classification number: H01L21/707