公开(公告)号：JP2014103271A

公开(公告)日：2014-06-05

申请号：JP2012254572

申请日：2012-11-20

申请人： Toshiba Corp ,  株式会社東芝

发明人： HAIMOTO TAKASHI ,  ICHIHARA REIKA ,  MITANI YUICHIRO ,  KOYAMA MASATO

IPC分类号： H01L27/105 ,  H01L45/00 ,  H01L49/00

CPC分类号： H01L45/12 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658

摘要： PROBLEM TO BE SOLVED: To provide a non-volatile storage device that allows being stably initialized by a low voltage and has uniform characteristics.SOLUTION: There is provided a non-volatile storage device including a semiconductor layer, a conductive layer, and a resistance change layer. The impurity concentration of the semiconductor layer is less than 1×10cm. The resistance change layer is provided between the semiconductor layer and the conductive layer, and contains stationary charges. The resistance change layer is reversibly transitionable between a first state and a second state having a higher resistance than the first state by at least either of a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer.

摘要翻译： 要解决的问题：提供允许通过低电压稳定地初始化并具有均匀特性的非易失性存储装置。解决方案：提供了一种非易失性存储装置，包括半导体层，导电层和电阻 改变层。 半导体层的杂质浓度小于1×10cm。 电阻变化层设置在半导体层与导电层之间，并含有固定电荷。 电阻变化层通过半导体层和导电层提供的电流中的至少一个以及通过半导体层施加的电压和导电的电压，可以在具有比第一状态更高的电阻的第一状态和第二状态之间可逆地转换 层。

公开(公告)号：JP2008177492A

公开(公告)日：2008-07-31

申请号：JP2007011698

申请日：2007-01-22

申请人： Toshiba Corp ,  株式会社東芝

发明人： SAKUMA KIWAMU ,  MATSUSHITA DAISUKE ,  KATO KOICHI ,  NAKASAKI YASUSHI ,  HIRANO IZUMI ,  MURAOKA KOICHI ,  MITANI YUICHIRO ,  FUKATSU SHIGETO ,  ITO TOSHIHIDE

IPC分类号： H01L21/8247 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent the deterioration of element characteristics even if it has a high dielectric insulating film, and its manufacturing method. SOLUTION: The device has a semiconductor substrate 1, a source region 8a and a drain region 8b formed apart from the semiconductor substrate, a first insulating film 3 formed on the semiconductor substrate between the source region and the drain region, a charge storage film 4 formed on the first insulating film, a second insulating film 5b formed of a high dielectric material formed on the charge storage film, a control gate electrode 6 formed on the second insulating film and silicon nitride layers 5a, 5c having the nitrogen bond of the threefold coordination of which at least one of second proximity atoms of nitrogen is nitrogen. At least either the charge storage film or the control gate electrode contains silicon, and the silicon nitride layer is formed at an interface between the second insulating film and one of the charge storage film and the control gate electrode containing silicon. COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：提供即使具有高介电绝缘膜也能够防止元件特性劣化的半导体器件及其制造方法。 解决方案：器件具有半导体衬底1，与半导体衬底分开形成的源极区域8a和漏极区域8b，形成在源区域和漏极区域之间的半导体衬底上的第一绝缘膜3，电荷 形成在第一绝缘膜上的保存膜4，形成在电荷存储膜上的高电介质材料形成的第二绝缘膜5b，形成在第二绝缘膜上的控制栅电极6和具有氮键的氮化硅层5a，5c 其中氮的第二接近原子中的至少一个为氮的三重配位。 电荷存储膜或控制栅电极中至少含有硅，并且氮化硅层形成在第二绝缘膜与电荷存储膜和含硅的控制栅电极之间的界面处。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008147390A

公开(公告)日：2008-06-26

申请号：JP2006332313

申请日：2006-12-08

申请人： Toshiba Corp ,  株式会社東芝

发明人： MITANI YUICHIRO ,  KOIKE MASAHIRO ,  NAKASAKI YASUSHI ,  MATSUSHITA DAISUKE

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To lower a program voltage, and also to reduce a stress-induced leakage current.
SOLUTION: A memory device includes a semiconductor substrate 1; a source region 8a and a drain region 8b separately formed on the semiconductor substrate; and a structure with a first insulating layer 3b
1 having an electron capture site, a second insulating layer 3a having no capture site, and a third insulating layer 3b
2 having the capture site laminated, and formed on the semiconductor substrate between the source region and the drain region. The electron capture site of the memory element has a first insulating film 3 positioned at the conduction band level energy lower than that of the first to the third insulating layers and higher than that of the silicon, a floating gate electrode 4 formed on the first insulating film, a second insulating film 5 formed on the floating gate electrode, and a control gate electrode 6 formed on the second insulating film.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：降低编程电压，并减少应力引起的漏电流。 存储器件包括半导体衬底1; 分别形成在半导体衬底上的源极区域8a和漏极区域8b; 以及具有具有电子捕获位点的第一绝缘层3b，不具有捕获位点的第二绝缘层3a和具有捕获位置的第三绝缘层3b 2 的结构 并且形成在源极区域和漏极区域之间的半导体衬底上。 存储元件的电子捕获位置具有第一绝缘膜3，该第一绝缘膜3位于比第一至第三绝缘层低的导带水平能量处，并且高于硅的导电能级，第一绝缘膜3形成在第一绝缘层上 膜，形成在浮栅上的第二绝缘膜5和形成在第二绝缘膜上的控制栅电极6。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004214305A

公开(公告)日：2004-07-29

申请号：JP2002380090

申请日：2002-12-27

申请人： Toshiba Corp ,  Toshiba Nanoanalysis Corp ,  東芝ナノアナリシス株式会社 ,  株式会社東芝

发明人： NAGAMINE MAKOTO ,  MITANI YUICHIRO ,  MORI SHINJI ,  SATO MUNEHARU

IPC分类号： H01L21/316 ,  H01L29/78

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device along with its manufacturing method, where the electric characteristics of an insulating film such as a gate oxide film is improved by introducing deuterium atoms of high binding energy into a film at high concentration.
SOLUTION: The method of manufacturing the semiconductor device includes a process for oxidizing the surface of a semiconductor in an oxidizing atmosphere. The oxidizing atmosphere contains the gas molecule composed of deuterium atoms, the gas molecule containing deuterium atoms and oxygen atoms, and the gas molecule containing oxygen atoms. The concentration of the gas molecule composed of the deuterium atoms is 0.01 molecule % or higher against the gas molecule containing the deuterium atoms and oxygen atoms.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2011216146A

公开(公告)日：2011-10-27

申请号：JP2010082875

申请日：2010-03-31

申请人： Toshiba Corp ,  株式会社東芝

发明人： MITANI YUICHIRO ,  MATSUSHITA DAISUKE ,  FUJII AKISUKE

IPC分类号： G11B9/04

CPC分类号： H01L45/1641 ,  G11C11/56 ,  G11C11/5614 ,  G11C11/5664 ,  G11C11/5685 ,  G11C2213/33 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233

摘要： PROBLEM TO BE SOLVED: To provide an information recording device that can highly accurately control achieving of multi levels.SOLUTION: The information recording device includes first and second electrodes 1a and 1b, a variable resistance layer 1c between the first and second electrodes, and a control circuit 2 which controls the resistance value between the first and second electrodes 1a and 1b to n (n is a natural number except 1) kinds of resistance value. The variable resistance layer 1c includes a high resistance material 1d filled between the first and second electrodes 1a and 1b and first, second, ..., nth low resistance particles 1e each having a resistance value lower than that of the high resistance material 1d and arranged from the first electrode 1a to the second electrode 1b in the high resistance material 1d, The control circuit 2 controls the n kinds of resistance value by short-circuiting the first electrode 1a and at least one of the first, second, ..., nth low resistance particles 1e.

摘要翻译： 要解决的问题：提供一种可以高精度地控制多级实现的信息记录装置。解决方案：信息记录装置包括第一和第二电极1a和1b，第一和第二电极之间的可变电阻层1c和 控制电路2，其将第一和第二电极1a和1b之间的电阻值控制为n（n是除了1之外的自然数）电阻值的种类。 可变电阻层1c包括填充在第一和第二电极1a和1b之间的高电阻材料1d和第一，第二，...第n个低电阻粒子1e，其电阻值低于高电阻材料1d的电阻值， 从高电阻材料1d中的第一电极1a到第二电极1b布置。控制电路2通过使第一电极1a短路和第一，第二电极1a中的至少一个来控​​制n种电阻值。 第n低电阻粒子1e。

公开(公告)号：JP2010226037A

公开(公告)日：2010-10-07

申请号：JP2009074427

申请日：2009-03-25

申请人： Toshiba Corp ,  株式会社東芝

发明人： HIRANO IZUMI ,  MITANI YUICHIRO ,  SHIMIZU TATSUO ,  NAKASAKI YASUSHI ,  SHODA AKIKO ,  FUKATSU SHIGETO ,  KOIKE MASAHIRO

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with MISFET which provides the longest life.
SOLUTION: The semiconductor device is provided with MISFET having: a semiconductor substrate 1 which has a semiconductor region 2 formed thereon; a source region 5a and a drain region 5b formed separately from each other in the semiconductor region; a gate insulating film 10 having a metal oxide layer 12 which is formed on a semiconductor region 3 between the source region and the drain region and which contains metal and oxygen; and a gate electrode 16 formed on the gate insulating film. The metal contained in the metal oxide layer is at least one chosen from Hf and Zr. Further, at least one element chosen from the elements Ru, Cr, Os, V, Fe, Tc, Nb, Ta is added to the metal oxide layer. The metal oxide layer has a charge trap which captures or emits a charge formed by the addition of the element. The density of the element in the metal oxide layer ranges from 1×10
15 cm
-3 to 2.96×10
20 cm
-3 . The charge trap is distributed so that it has a peak in the semiconductor region side rather than the center of the metal oxide layer.
COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：提供一种配备有提供最长寿命的MISFET的半导体器件。 解决方案：半导体器件设置有MISFET，其具有：半导体衬底1，其上形成有半导体区域2; 在半导体区域中彼此分开形成的源极区域5a和漏极区域5b; 具有金属氧化物层12的栅极绝缘膜10，该金属氧化物层12形成在源极区域和漏极区域之间并且含有金属和氧气的半导体区域3上; 以及形成在栅极绝缘膜上的栅电极16。 包含在金属氧化物层中的金属是选自Hf和Zr中的至少一种。 此外，从元素Ru，Cr，Os，V，Fe，Tc，Nb，Ta中选择的至少一种元素添加到金属氧化物层。 金属氧化物层具有捕获或发射通过添加元素形成的电荷的电荷陷阱。 金属氧化物层中的元素的密度在1×10 cm -3 / SP至-296×10 20 3 。 分配电荷阱使得其在半导体区域侧而不是金属氧化物层的中心具有峰值。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010177323A

公开(公告)日：2010-08-12

申请号：JP2009016285

申请日：2009-01-28

申请人： Toshiba Corp ,  株式会社東芝

发明人： MATSUSHITA DAISUKE ,  OBA RYUJI ,  MITANI YUICHIRO

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0466 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To prevent degradation in electric charge holding characteristics as much as possible even if micronization is done.
SOLUTION: The nonvolatile semiconductor memory device includes a first insulating film 2 formed on a semiconductor substrate 1, an electric charge trap film 4 containing a first nitride layer 4a formed on the first insulating film, a first oxynitride layer 4b formed on the first nitride layer, and a second nitride layer 4c formed on the first oxynitride layer, a second insulating film 10 formed on the electric charge trap film, and control gate 11 formed on the second insulating film.
COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：即使进行微粉化，也尽可能地防止电荷保持特性的降低。 解决方案：非易失性半导体存储器件包括形成在半导体衬底1上的第一绝缘膜2，包含形成在第一绝缘膜上的第一氮化物层4a的电荷陷阱膜4，形成在第一绝缘膜上的第一氧氮化物层4b 第一氮化物层和形成在第一氧氮化物层上的第二氮化物层4c，形成在电荷捕获膜上的第二绝缘膜10和形成在第二绝缘膜上的控制栅极11。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009238903A

公开(公告)日：2009-10-15

申请号：JP2008081021

申请日：2008-03-26

申请人： Toshiba Corp ,  株式会社東芝

发明人： KAI WAKANA ,  MORI SHINJI ,  KAI TETSUYA ,  OZAWA YOSHIO ,  MIZUSHIMA ICHIRO ,  SATO TSUTOMU ,  MATSUBA HIROSHI ,  MITANI YUICHIRO

IPC分类号： H01L21/8247 ,  H01L21/316 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device can improve injection efficiency of charge into a charge storage layer; and a manufacturing method of the same.
SOLUTION: This manufacturing method of the semiconductor device provided with a first insulation film formed on a semiconductor substrate, the charge storage layer formed on the first insulation film, a second insulation film formed on the charge storage layer, and a control gate electrode formed on the second insulation film includes processes of: forming the first insulation film 204; forming a lower insulation layer 201; forming a germanium-containing layer 202 on the lower insulation layer 201; forming an intermediate insulation layer 202a by reaction among the germanium-containing layer 202, silicon and oxygen; and forming an upper insulation layer 203 on the intermediate insulation layer 202a.
COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：提供半导体器件可以将电荷的注入效率提高到电荷存储层中; 及其制造方法。 解决方案：该半导体器件的制造方法具有形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及控制栅极 形成在第二绝缘膜上的电极包括：形成第一绝缘膜204的工艺; 形成下绝缘层201; 在下绝缘层201上形成含锗层202; 通过含锗层202，硅和氧之间的反应形成中间绝缘层202a; 并在中间绝缘层202a上形成上绝缘层203。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009231373A

公开(公告)日：2009-10-08

申请号：JP2008072148

申请日：2008-03-19

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  MITANI YUICHIRO ,  NAKASAKI YASUSHI ,  KOYAMA MASATO

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/11568

摘要： PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory device having a tunnel insulation film capable of reducing leakage current in a low electric field even if film thickness (EOT) converted to an oxide film is thinned and also increasing the leakage current in a high electric field. SOLUTION: A memory element is provided, which comprises a semiconductor substrate 1, a source region 2a and a drain region 2b formed separately on the semiconductor substrate, a first insulation film 3 formed on the semiconductor substrate between the source region and the drain region, containing insulation layers 8 and 9 having a site formed by adding an element different from that of a base material for capturing and emitting electrons and having different dielectric constants with the site for capturing and emitting the electrons at a level higher than a Fermi level of the material constituting the semiconductor substrate, a charge storage film 4 formed on the first insulation film, a second insulation film 5 formed on the charge storage film and a control gate electrode 6 formed on the second insulation film. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 解决的问题为了获得具有能够减小低电场中的漏电流的隧道绝缘膜的非易失性半导体存储器件，即使转换为氧化膜的膜厚度（EOT）变薄并且还增加漏电流 在高电场。 解决方案：提供一种存储元件，其包括在半导体衬底上分开形成的半导体衬底1，源极区域2a和漏极区域2b，形成在半导体衬底之间的源区域和 漏极区域，包含绝缘层8和9，其具有通过添加与用于捕获和发射电子的基底材料不同的元素并且具有不同介电常数的元件与用于捕获和发射电子的位置形成的位置形成，所述位置高于费米 构成半导体衬底的材料的高度，形成在第一绝缘膜上的电荷存储膜4，形成在电荷存储膜上的第二绝缘膜5和形成在第二绝缘膜上的控制栅电极6。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009176803A

公开(公告)日：2009-08-06

申请号：JP2008011308

申请日：2008-01-22

申请人： Toshiba Corp ,  株式会社東芝

发明人： MATSUSHITA DAISUKE ,  MITANI YUICHIRO

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3145 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To obtain a high quality insulating film in which a defect is hard to occur, and to reduce leakage current. SOLUTION: A manufacturing method of a semiconductor device includes a step of forming an amorphous silicon layer on an insulating layer 2, a step of introducing oxygen to the amorphous silicon layer, and a step of forming a silicon oxynitride layer 3. COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 要解决的问题：为了获得难以发生缺陷的高质量绝缘膜，并且减少漏电流。 解决方案：半导体器件的制造方法包括在绝缘层2上形成非晶硅层的步骤，向非晶硅层引入氧的步骤和形成氮氧化硅层3的步骤。 P>版权所有（C）2009，JPO＆INPIT