摘要:
PROBLEM TO BE SOLVED: To provide a semiconductor device with uniform display characteristics having reduced fluctuation in threshold voltage while an influence of plasma damage is reduced during a manufacturing process of the semiconductor device.SOLUTION: The semiconductor device includes a flattened layer 113 on a transistor and a barrier layer 112 provided on the upper or lower surface of the flattened layer and also preventing moisture or degassing components from diffusing from the flattened layer, and uses a device structure effective for reducing plasma damage to the flattened layer by devising a positional relation between the flattened layer and the barrier layer. A combination with a novel structure as a structure of a pixel electrode also contributes to improve brightness or the like.
摘要:
Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.
摘要:
A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm-3 to 2.96×1020 cm-3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.