公开(公告)号：JP2012099510A

公开(公告)日：2012-05-24

申请号：JP2009055267

申请日：2009-03-09

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  TATSUMURA KOSUKE

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： PROBLEM TO BE SOLVED: To form an n-type impurity region composed of carriers of ultra-shallow and high concentration in a Ge semiconductor layer.SOLUTION: A semiconductor device comprises: a semiconductor substrate having one conductivity type of n type or p type; a pair of impurity diffusion regions that are selectively provided on a surface of the semiconductor substrate and have a different conductivity type from the one conductivity type; a gate insulating layer that is sandwiched between the pair of the impurity diffusion regions and is provided on the semiconductor substrate; and a gate electrode provided on the gate insulating layer. A portion of the pair of the impurity diffusion regions has the same conductivity type as the impurity containing the substrate and has a higher impurity concentration than that of the substrate.

摘要翻译： 要解决的问题：在Ge半导体层中形成由超浅和高浓度的载流子构成的n型杂质区。 解决方案：半导体器件包括：具有n型或p型导电类型的一种半导体衬底; 一对杂质扩散区，其选择性地设置在半导体衬底的表面上并且具有与一种导电类型不同的导电类型; 栅极绝缘层，被夹在所述一对所述杂质扩散区域之间并设置在所述半导体衬底上; 以及设置在栅极绝缘层上的栅电极。 一对杂质扩散区域的一部分具有与含有衬底的杂质相同的导电类型，并且具有比衬底更高的杂质浓度。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010226037A

公开(公告)日：2010-10-07

申请号：JP2009074427

申请日：2009-03-25

申请人： Toshiba Corp ,  株式会社東芝

发明人： HIRANO IZUMI ,  MITANI YUICHIRO ,  SHIMIZU TATSUO ,  NAKASAKI YASUSHI ,  SHODA AKIKO ,  FUKATSU SHIGETO ,  KOIKE MASAHIRO

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with MISFET which provides the longest life.
SOLUTION: The semiconductor device is provided with MISFET having: a semiconductor substrate 1 which has a semiconductor region 2 formed thereon; a source region 5a and a drain region 5b formed separately from each other in the semiconductor region; a gate insulating film 10 having a metal oxide layer 12 which is formed on a semiconductor region 3 between the source region and the drain region and which contains metal and oxygen; and a gate electrode 16 formed on the gate insulating film. The metal contained in the metal oxide layer is at least one chosen from Hf and Zr. Further, at least one element chosen from the elements Ru, Cr, Os, V, Fe, Tc, Nb, Ta is added to the metal oxide layer. The metal oxide layer has a charge trap which captures or emits a charge formed by the addition of the element. The density of the element in the metal oxide layer ranges from 1×10
15 cm
-3 to 2.96×10
20 cm
-3 . The charge trap is distributed so that it has a peak in the semiconductor region side rather than the center of the metal oxide layer.
COPYRIGHT: (C)2011,JPO&INPIT

摘要翻译： 要解决的问题：提供一种配备有提供最长寿命的MISFET的半导体器件。 解决方案：半导体器件设置有MISFET，其具有：半导体衬底1，其上形成有半导体区域2; 在半导体区域中彼此分开形成的源极区域5a和漏极区域5b; 具有金属氧化物层12的栅极绝缘膜10，该金属氧化物层12形成在源极区域和漏极区域之间并且含有金属和氧气的半导体区域3上; 以及形成在栅极绝缘膜上的栅电极16。 包含在金属氧化物层中的金属是选自Hf和Zr中的至少一种。 此外，从元素Ru，Cr，Os，V，Fe，Tc，Nb，Ta中选择的至少一种元素添加到金属氧化物层。 金属氧化物层具有捕获或发射通过添加元素形成的电荷的电荷陷阱。 金属氧化物层中的元素的密度在1×10 cm -3 / SP至-296×10 20 3 。 分配电荷阱使得其在半导体区域侧而不是金属氧化物层的中心具有峰值。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009231373A

公开(公告)日：2009-10-08

申请号：JP2008072148

申请日：2008-03-19

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  MITANI YUICHIRO ,  NAKASAKI YASUSHI ,  KOYAMA MASATO

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/11568

摘要： PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory device having a tunnel insulation film capable of reducing leakage current in a low electric field even if film thickness (EOT) converted to an oxide film is thinned and also increasing the leakage current in a high electric field. SOLUTION: A memory element is provided, which comprises a semiconductor substrate 1, a source region 2a and a drain region 2b formed separately on the semiconductor substrate, a first insulation film 3 formed on the semiconductor substrate between the source region and the drain region, containing insulation layers 8 and 9 having a site formed by adding an element different from that of a base material for capturing and emitting electrons and having different dielectric constants with the site for capturing and emitting the electrons at a level higher than a Fermi level of the material constituting the semiconductor substrate, a charge storage film 4 formed on the first insulation film, a second insulation film 5 formed on the charge storage film and a control gate electrode 6 formed on the second insulation film. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 解决的问题为了获得具有能够减小低电场中的漏电流的隧道绝缘膜的非易失性半导体存储器件，即使转换为氧化膜的膜厚度（EOT）变薄并且还增加漏电流 在高电场。 解决方案：提供一种存储元件，其包括在半导体衬底上分开形成的半导体衬底1，源极区域2a和漏极区域2b，形成在半导体衬底之间的源区域和 漏极区域，包含绝缘层8和9，其具有通过添加与用于捕获和发射电子的基底材料不同的元素并且具有不同介电常数的元件与用于捕获和发射电子的位置形成的位置形成，所述位置高于费米 构成半导体衬底的材料的高度，形成在第一绝缘膜上的电荷存储膜4，形成在电荷存储膜上的第二绝缘膜5和形成在第二绝缘膜上的控制栅电极6。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007273548A

公开(公告)日：2007-10-18

申请号：JP2006094630

申请日：2006-03-30

申请人： Toshiba Corp ,  株式会社東芝

发明人： INO TSUNEHIRO ,  KOIKE MASAHIRO ,  KOYAMA MASATO

IPC分类号： H01L45/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L49/00

CPC分类号： G11C13/0007

摘要： PROBLEM TO BE SOLVED: To provide a resistance changing element capable of reducing the variation of operating voltage upon forming.
SOLUTION: A resistance changing film 4, in which a metal oxide or a metallic oxynitride containing at least either one of Zr and Hf as a principal constituent is provided with fluorite structure, and a pair of first and second electrodes 2, 6 provided so as to pinch the resistance changing film are provided. The crystal structure of the resistance changing film is provided with Bevan cluster in a part or the whole of it and when V shows a vacancy, in which negative ion is not existing in a negative ion site in the fluorite type crystal structure, M shows the metallic element of the metal oxide or the metallic oxynitride and S shows the maximum octahedron type cavity site in the fluorite type crystal structure, the direction of array of a straight chain type continuous chain of (-S-V-M-V-S-) in the unit cell of the Bevan cluster is provided with the direction of crystal substantially orthogonal to the principal surface of the film.
COPYRIGHT: (C)2008,JPO&INPIT

摘要翻译： 要解决的问题：提供一种能够在成形时减小工作电压的变化的电阻变化元件。 解决方案：将以Zr和Hf中的至少一种作为主要成分的金属氧化物或金属氮氧化物设置有萤石结构的电阻变化膜4和一对第一和第二电极2,6 设置为夹紧电阻变化膜。 电阻变化膜的晶体结构部分或全部设置有Bevan簇，当V表示在萤石型晶体结构的负离子位置不存在负离子的空位时，M表示 金属氧化物的金属元素或金属氮氧化物，S表示萤石型晶体结构中最大的八面体型腔部位，Bevan的晶胞中的（-SVMVS-）直链型连续链阵列的方向 簇具有与膜的主表面基本正交的晶体的方向。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2010062387A

公开(公告)日：2010-03-18

申请号：JP2008227418

申请日：2008-09-04

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  MITANI YUICHIRO ,  SHIMIZU TATSUO ,  YASUDA NAOKI ,  NAKASAKI YASUSHI ,  NISHIYAMA AKIRA

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/513

摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a tunnel insulating film, capable of reducing leakage current in a low electric field even if thinning EOT and also capable of increasing the leakage current of holes in a high electric field. SOLUTION: The device includes a storage element having: a semiconductor substrate 1; a source region 2a and a drain region 2b separately formed in the semiconductor substrate; and a first insulating layer 3 formed on an area between the source region and the drain region of the semiconductor substrate; a charge storage film 4 formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode 6 formed on the second insulating film, wherein the first insulating film 3 includes a first insulating layer and a second insulating layer which is formed on the first insulating layer, has a dielectric constant higher than that of the first insulating layer, and has a first site for capturing or emitting holes, formed by being doped with an element that is different from that of a base material. COPYRIGHT: (C)2010,JPO&INPIT

摘要翻译： 要解决的问题：为了提供一种具有隧道绝缘膜的非易失性半导体存储装置，即使减少EOT也能够降低低电场中的漏电流，并且还能够增加高电场中的空穴的漏电流 。 解决方案：该器件包括具有：半导体衬底1的存储元件; 分别形成在半导体衬底中的源极区域2a和漏极区域2b; 以及形成在所述半导体衬底的源极区域和漏极区域之间的区域上的第一绝缘层3; 形成在第一绝缘膜上的电荷存储膜4; 形成在电荷存储膜上的第二绝缘膜; 以及形成在第二绝缘膜上的控制栅电极6，其中第一绝缘膜3包括形成在第一绝缘层上的第一绝缘层和第二绝缘层，其介电常数高于第一绝缘层的介电常数 并且具有用于捕获或发射孔的第一位点，其通过掺杂有与基底材料的元素不同的元素而形成。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009170929A

公开(公告)日：2009-07-30

申请号：JP2009055342

申请日：2009-03-09

申请人： Toshiba Corp ,  株式会社東芝

发明人： NARA AKIKO ,  KOIKE MASAHIRO ,  MITANI YUICHIRO

IPC分类号： H01L21/8247 ,  H01L21/316 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a stack gate structure comprising a floating gate electrode and a control gate electrode that are laminated, which is improved in tunnel insulating film and inter-electrode insulating film.
SOLUTION: The nonvolatile semiconductor memory device includes: a floating gate electrode 12 which is selectively formed above a main surface of a first conduction type semiconductor substrate 10 via a tunnel insulating film 11; a control electrode 14 formed above the floating gate electrode 12 via an inter-electrode insulating film 13; and a second conduction type source/drain region 15 formed on the main surface of the substrate 10 in correspondence with respective gate electrodes 12, 14, wherein the tunnel insulating film 11 is a dielectric film containing at least two kinds of metallic elements (Al, Hf) and oxygen, with the composition of the metallic elements continuously varying with respect to the direction of the film thickness and having a symmetrical distribution.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 解决的问题：为了提供一种具有堆叠栅极结构的非易失性半导体存储器件，该堆叠栅极结构包括层叠的浮置栅极电极和控制栅电极，其在隧道绝缘膜和电极间绝缘膜中得到改善。 解决方案：非易失性半导体存储器件包括：浮栅电极12，其通过隧道绝缘膜11选择性地形成在第一导电型半导体衬底10的主表面上; 经由电极间绝缘膜13形成在浮栅电极12的上方的控制电极14; 以及与各个栅电极12,14对应地形成在基板10的主表面上的第二导电型源极/漏极区域15，其中隧道绝缘膜11是包含至少两种金属元素（Al， Hf）和氧，金属元素的组成相对于膜厚度的方向连续变化并具有对称分布。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009059964A

公开(公告)日：2009-03-19

申请号：JP2007226991

申请日：2007-08-31

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  TATSUMURA KOSUKE ,  KAMATA YOSHIKI ,  KOYAMA MASATO ,  NAKASAKI YASUSHI ,  SUZUKI MASAMICHI

IPC分类号： H01L21/316 ,  H01L21/283 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus that improves interfacial characteristics of an insulating film having a metal element.
SOLUTION: The method includes a step of forming a structure wherein a lower layer, a Ge layer, a Ge oxide layer, and an upper layer are stacked in order, and a step of removing the Ge oxide layer and Ge layer using a heat treatment to bond the upper layer and the lower layer directly to each other. The upper layer or the lower layer is formed of an insulator having a metal element.
COPYRIGHT: (C)2009,JPO&INPIT

摘要翻译： 解决的问题：提供一种提高具有金属元素的绝缘膜的界面特性的半导体装置的制造方法。 解决方案：该方法包括：依次堆叠下层，Ge层，Ge氧化物层和上层的结构的步骤，以及使用以下步骤除去Ge氧化物层和Ge层的步骤 将上层和下层彼此直接接合的热处理。 上层或下层由具有金属元素的绝缘体形成。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006005006A

公开(公告)日：2006-01-05

申请号：JP2004177191

申请日：2004-06-15

申请人： Toshiba Corp ,  株式会社東芝

发明人： NARA AKIKO ,  KOIKE MASAHIRO ,  MITANI YUICHIRO

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7883

摘要： PROBLEM TO BE SOLVED: To reduce a leakage current even in either high electric field of both a positive electrode and a negative electrode, and to inhibit the leakage current in a wide electric-field range from a low electric field to a high electric field difficult in a single high dielectric film.
SOLUTION: A nonvolatile semiconductor memory comprises a floating gate electrode 12 selectively formed on the main surface of a first conductivity type semiconductor substrate 10 through a tunnel insulating film 11, and a control gate electrode 14 formed on the floating gate electrode 12 through an inter-electrode insulating film 13. The nonvolatile semiconductor memory further has second conductivity type source-drain regions 15 formed on the main surface of the substrate in response to each gate electrode 12 and 14. In the nonvolatile semiconductor memory, the inter-electrode insulating film 13 has three layers or more of a laminated structure composed of two kinds or more of high dielectric materials 13a, 13b and 13c.
COPYRIGHT: (C)2006,JPO&NCIPI

摘要翻译： 要解决的问题：即使在正电极和负电极的高电场中也能够减小漏电流，并且在从低电场到高电平的宽电场范围内抑制泄漏电流 电场难以在单个高介电膜中。 解决方案：非易失性半导体存储器包括通过隧道绝缘膜11选择性地形成在第一导电类型半导体衬底10的主表面上的浮栅电极12和形成在浮栅电极12上的控制栅极14 电极间绝缘膜13.非易失性半导体存储器还具有响应于每个栅电极12和14形成在基板的主表面上的第二导电型源极 - 漏极区域15.在非易失性半导体存储器中， 绝缘膜13具有由两种以上的高介电材料13a，13b，13c构成的层叠结构的三层以上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004241725A

公开(公告)日：2004-08-26

申请号：JP2003031466

申请日：2003-02-07

申请人： Toshiba Corp ,  株式会社東芝

发明人： KOIKE MASAHIRO ,  KOYAMA MASATO ,  INO TSUNEHIRO ,  KAMIMUTA YUICHI ,  TAKASHIMA AKIRA ,  SUZUKI MASAMICHI ,  NISHIYAMA AKIRA

IPC分类号： C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/283 ,  H01L21/318 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/517 ,  H01L29/518

摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device constituted of an insulating film composed of a nitrogen-containing metal silicate film, of which crystallization can be inhibited, which has a sufficiently high dielectric constant and a leakage current from which is made lower than that from an oxide film.
SOLUTION: The semiconductor device has a substrate (50), an insulating film (90) containing a metal, Si, N and 0 and an electrode (180) formed on the insulating film. Metal-N bonds contained in the insulating film are made larger than the sum of metal-metal bonds and metal-Si bonds.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2014220274A

公开(公告)日：2014-11-20

申请号：JP2013096286

申请日：2013-05-01

申请人： 株式会社東芝 ,  Toshiba Corp

发明人： KOIKE MASAHIRO ,  KAMIMUTA YUICHI ,  TEZUKA TSUTOMU

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/28052 ,  H01L21/2807 ,  H01L21/28518 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/78

摘要： 【課題】Geを主成分とする半導体層上に金属Ge化合物の単結晶層を形成することができ、且つ金属Ge化合物層と半導体層との界面平坦性の向上をはかる。【解決手段】Geを主成分とする半導体層10上に金属Ge化合物層16を形成した半導体装置であって、金属Ge化合物領域16と半導体層10との界面付近にSnを含有し、金属Ge化合物領域16が半導体層10の表面上にエピタキシャル成長している。【選択図】図1

摘要翻译： 要解决的问题：使得能够在具有Ge作为主要成分的半导体层上形成金属Ge化合物的单晶层，并提高金属Ge化合物和半导体层之间的界面平坦度。解决方案：半导体器件包括 形成在具有Ge作为主要成分的半导体层10上的金属Ge化合物层16。 Sn被包含在金属Ge化合物层16和半导体层10之间的界面附近。金属Ge化合物层16在半导体层10的表面上外延生长。